| ID |
Date |
Author |
Type |
Category |
Subject |
Text |
 |
|
32
|
12 Jul 2019 01:27 |
Marco Rescigno | Configuration | | MB1 test in proto-0 setup/1 | Changed custom size to 500 (20 us), tested
ok run 681 |
|
|
5
|
11 Jan 2019 11:07 |
Thomas | Routine | Digitizer | Data corruption for ADC channels | I modified the analyzer so that it shows data
from all four modules.
|
|
|
7
|
21 Jan 2019 13:05 |
Thomas, Pierre | Routine | Digitizer | Tests of V1725 baseline and triggering | A little progress on a couple fronts:
1) We got the baseline DAC setting working |
|
|
15
|
05 Mar 2019 10:36 |
Thomas | Routine | Digitizer | Switched to standard V1725 firmware | It turns out that the ZLE V1725 firmware we
are using only supports reading out up to
4000 samples per channel.
|
|
|
70
|
05 Nov 2019 01:22 |
Ben Smith | Configuration | Digitizer | V1725 board config | The V1725s have been changed to have board
config 0x50 rather than 0x10. This means
that they will now trigger on the leading |
|
|
114
|
11 Nov 2019 00:47 |
Yi / Edgar | Problem Fixed | Digitizer | Problem fixed by restarting the VME crate | |
|
|
119
|
12 Nov 2019 00:16 |
Yi Wang | Problem | Digitizer | V1725 error, runs keep crashing | 09:15:33.955 2019/11/12 [feov1725MTI00,ERROR]
[feoV1725.cxx:663:link_thread,ERROR] Exiting
thread 3 with error |
|
|
120
|
12 Nov 2019 00:23 |
Ben Smith | Problem | Digitizer | V1725 error, runs keep crashing | It looks like there's a memory leak in the
high voltage driver, and we were running
out of memory (using a lot of swap). That |
|
|
4
|
09 Jan 2019 12:22 |
Thomas | Routine | General | V1725 LVDS outputs | Pierre figured out that NIM crate not working.
We now see LVDS outputs from the individual
channels firing.
|
|
|
14
|
19 Feb 2019 16:26 |
Pierre-A. | Configuration | General | Overall HW configuration | For Reference,
I put a simple schematic for the
Trigger/Run control. |
|
|
17
|
06 Mar 2019 14:16 |
Thomas | Routine | General | Retested the chronobox trigger logic | I retested the chronobox trigger generation:
1) Inserting moderate sized pulse into channel |
|
|
27
|
08 Apr 2019 08:31 |
Thomas | Routine | General | General work - day 1 at CERN | Notes on day:
1) Fixed the problem with the network interfaces. |
|
|
28
|
10 Apr 2019 05:40 |
Thomas | Routine | General | General work - day 3 at CERN | Several points:
1) Gave a series of tutorial on DAQ to DS |
|
|
34
|
12 Jul 2019 06:01 |
Marco Rescigno | Routine | General | Run 703 | Run 703 is being writte on disk.
16 channels of board 00.
Laser trigger at 10 Hz |
|
|
35
|
12 Jul 2019 07:58 |
Marco Rescigno | Routine | General | MB1 test in proto-0 setup/day 2 | Implemented a simple charge integration
on the midas display, most of the channels
look almost as good as this one. |
|
|
36
|
12 Jul 2019 11:34 |
Marco Rescigno | Routine | General | MB1 test in proto-0 setup/2 Run 718 | Run 718 has 25 channel readout Board 0
ch 0-15 and Board 0 ch 0-7.
Laser triggered, some noise, maybe |
|
|
37
|
13 Jul 2019 14:50 |
Marco Rescigno | Routine | General | Long Laser run on disk | Run 747 , 250 k events
as requested by alessandro 40%
post trigger, acquisition window 16 us. |
|
|
38
|
16 Jul 2019 01:58 |
Marco Rescigno | Routine | General | Run 766 (Laser) | Laser Run with Vbias=65 V , new recommended
value from PE group
500 k events acquired |
|
|
39
|
16 Jul 2019 02:39 |
Marco Rescigno | Routine | General | run 771, scintillation events triggering on ch11 and ch12 of board0 | Trigger setup with a threshold of 1500
ADC count wrt to baseline, on just two channels.
This is also to limit the trigger |
|
|
41
|
16 Jul 2019 03:17 |
Marco Rescigno | Routine | General | run 772, scintillation events triggering on all channels | Majority of 5, threshold at 1000 ADC count,
13 channels enabled (10 trigger signals)
50 Hz, 30 us window. |
|