The FEB64 board handles 64 MPPC Silicon PM mounted in the FGD detector. Its main purpose is to read the 64 (76) MPPC channels. The information is stored in the AFTER SCA chip (Analog memory). For every trigger, each cell of the analog memory (76x512 cells) is digitized, the digital value representing the amplitude at a given time (20Msps) is transmitted to the CMB card. In parallel to its main function, the FE64 has a "slow control" section which run completely independently from the data acquisition section and provides card condition status, board and internal detector temperature monitoring and control/monitoring of the high voltage fed to the MPPCs.
This card is located in each "crate" mounted on the surrounding structure of each FGD (24 crates per FGD). Each crate contains 4 FEB64 cards.