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(SerDes/SGMII code viol pkt cnt) 0x%08X 0x0A018: HRMPC (Header redir missed pkt count) 0x%08X 0x0%02X: SRRCTL%d (Split and replic rx ctl%d) 0x%08X 0x0%02X: PSRTYPE%d (Packet split receive type%d) 0x%08X 0x0%02X: RDBAL%d (Rx desc base addr low%d) 0x%08X 0x0%02X: RDBAH%d (Rx desc base addr high%d) 0x%08X 0x0%02X: RDLEN%d (Rx descriptor length%d) 0x%08X 0x0%02X: RDH%d (Rx descriptor head%d) 0x%08X 0x0%02X: RDT%d (Rx descriptor tail%d) 0x%08X 0x0%02X: RXDCTL%d (Rx descriptor control%d) 0x%08X 0x0%02X: EITR%d (Interrupt throttle%d) 0x%08X 0x0%02X: IMIR%d (Immediate interrupt Rx%d) 0x%08X 0x0%02X: IMIREXT%d (Immediate interr Rx extended%d) 0x%08X 0x0%02X: RAL%02d (Receive address low%02d) 0x%08X 0x0%02X: RAH%02d (Receive address high%02d) 0x%08X 0x0%02X: TDBAL%d (Tx desc base address low%d) 0x%08X 0x0%02X: TDBAH%d (Tx desc base address high%d) 0x%08X 0x0%02X: TDLEN%d (Tx descriptor length%d) 0x%08X 0x0%02X: TDH%d (Transmit descriptor head%d) 0x%08X 0x0%02X: TDT%d (Transmit descriptor tail%d) 0x%08X 0x0%02X: TXDCTL%d (Transmit descriptor control%d) 0x%08X 0x0%02X: TDWBAL%d (Tx desc complete wb addr low%d) 0x%08X 0x0%02X: TDWBAH%d (Tx desc complete wb addr hi%d) 0x%08X 0x0%02X: DCA_TXCTRL%d (Tx DCA control%d) 0x%08X 0x0%02X: IP4AT%d (IPv4 address table%d) 0x%08X 0x0%02X: IP6AT%d (IPv6 address table%d) 0x%08X 0x0%02X: WUPM%02d (Wake up packet memory%02d) 0x%08X 0x0%02X: FFMT%03d (Flexible filter mask table%03d) 0x%08X 0x0%02X: FFVT%03d (Flexible filter value table%03d) 0x%08X 0x0%02X: FFLT%d (Flexible filter length table%d) 0x%08X 0x03410: TDFH (Tx data FIFO head) 0x%08X 0x03418: TDFT (Tx data FIFO tail) 0x%08X 0x03420: TDFHS (Tx data FIFO head saved) 0x%08X 0x03430: TDFPC (Tx data FIFO packet count) 0x%08X 0x%04lx: %-16s 0x%08x addr_lowaddr_highhash_table_highhash_table_lowr_des_startx_des_startr_buff_sizeecntrlieventimaskivecr_des_activex_des_activemii_datamii_speedr_boundr_fstartx_fstartfun_coder_cntrlr_hashx_cntrlMAL%d Registers -----------------CFG = 0x%08x ESR = 0x%08x IER = 0x%08x TX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x RX|CASR = 0x%08x CARR = 0x%08x EOBISR = 0x%08x DEIR = 0x%08x TX| RX| CTP%d = 0x%08x EMAC%d Registers MR0 = 0x%08x MR1 = 0x%08x RMR = 0x%08x ISR = 0x%08x ISER = 0x%08x TMR0 = 0x%08x TMR1 = 0x%08x TRTR = 0x%08x RWMR = 0x%08x IAR = %04x%08x LSA = %04x%08x IAHT = 0x%04x 0x%04x 0x%04x 0x%04x GAHT = 0x%04x 0x%04x 0x%04x 0x%04x VTPID = 0x%04x VTCI = 0x%04x IPGVR = 0x%04x STACR = 0x%08x OCTX = 0x%08x OCRX = 0x%08x RCBS%d = 0x%08x (%d) IPCR = 0x%08x ZMII%d Registers FER = %08x SSR = %08x SMIISR = %08x RGMII%d Registers FER = %08x SSR = %08x TAH%d Registers REVID = %08x MR = %08x TSR = %08x SSR0 = %08x SSR1 = %08x SSR2 = %08x SSR3 = %08x SSR4 = %08x SSR5 = %08x 0x00000: CTRL0 (Device control register) 0x%08X Link reset: %s VLAN mode: %s 0x00010: STATUS (Device status register) 0x%08X Link up: %s Bus type: %s Bus speed: %s Bus width: %s 0x00100: RCTL (Receive control register) 0x%08X Receiver: %s Store bad packets: %s Unicast promiscuous: %s Multicast promiscuous: %s Descriptor minimum threshold size: %s Broadcast accept mode: %s VLAN filter: %s Cononical form indicator: %s 0x00120: RDLEN (Receive desc length) 0x%08X 0x00128: RDH (Receive desc head) 0x%08X 0x00130: RDT (Receive desc tail) 0x%08X 0x00138: RDTR (Receive delay timer) 0x%08X 0x00600: TCTL (Transmit ctrl register) 0x%08X Transmitter: %s 0x00610: TDLEN (Transmit desc length) 0x%08X 0x00618: TDH (Transmit desc head) 0x%08X 0x00620: TDT (Transmit desc tail) 0x%08X 0x00628: TIDV (Transmit delay timer) 0x%08X updown10G1G0x042A4: LINKS (Link Status register) 0x%08X Link Status: %s Link Speed: %s 0x05080: FCTRL (Filter Control register) 0x%08X Broadcast Accept: %s Unicast Promiscuous: %s Multicast Promiscuous: %s Store Bad Packets: %s Receive Flow Control Packets: %s Receive Priority Flow Control Packets: %s Discard Pause Frames: %s Pass MAC Control Frames: %s 0x04294: MFLCN (TabMAC Flow Control register) 0x%08X Receive Flow Control Packets: %s Discard Pause Frames: %s Pass MAC Control Frames: %s Receive Priority Flow Control Packets: %s 0x05088: VLNCTRL (VLAN Control register) 0x%08X VLAN Mode: %s VLAN Filter: %s 0x02100: SRRCTL0 (Split and Replic Rx Control 0) 0x%08X Receive Buffer Size: %uKB 0x03D00: RMCS (Receive Music Control register) 0x%08X Transmit Flow Control: %s Priority Flow Control: %s 0x04250: HLREG0 (Highlander Control 0 register) 0x%08X Transmit CRC: %s Receive CRC Strip: %s Jumbo Frames: %s Pad Short Frames: %s Loopback: %s 0x00000: CTRL (Device Control) 0x%08X 0x00008: STATUS (Device Status) 0x%08X 0x00018: CTRL_EXT (Extended Device Control) 0x%08X 0x00020: ESDP (Extended SDP Control) 0x%08X 0x00028: EODSDP (Extended OD SDP Control) 0x%08X 0x00200: LEDCTL (LED Control) 0x%08X 0x00048: FRTIMER (Free Running Timer) 0x%08X 0x0004C: TCPTIMER (TCP Timer) 0x%08X 0x10010: EEC (EEPROM/Flash Control) 0x%08X 0x10014: EERD (EEPROM Read) 0x%08X 0x1001C: FLA (Flash Access) 0x%08X 0x10110: EEMNGCTL (Manageability EEPROM Control) 0x%08X 0x10114: EEMNGDATA (Manageability EEPROM R/W Data) 0x%08X 0x10110: FLMNGCTL (Manageability Flash Control) 0x%08X 0x1011C: FLMNGDATA (Manageability Flash Read Data) 0x%08X 0x10120: FLMNGCNT (Manageability Flash Read Count) 0x%08X 0x1013C: FLOP (Flash Opcode) 0x%08X 0x10200: GRC (General Receive Control) 0x%08X 0x00800: EICR (Extended Interrupt Cause) 0x%08X 0x00808: EICS (Extended Interrupt Cause Set) 0x%08X 0x00880: EIMS (Extended Interr. Mask Set/Read) 0x%08X 0x00888: EIMC (Extended Interrupt Mask Clear) 0x%08X 0x00810: EIAC (Extended Interrupt Auto Clear) 0x%08X 0x00890: EIAM (Extended Interr. Auto Mask EN) 0x%08X 0x00820: EITR0 (Extended Interrupt Throttle 0) 0x%08X 0x00900: IVAR0 (Interrupt Vector Allocation 0) 0x%08X 0x00000: MSIXT (MSI-X Table) 0x%08X 0x02000: MSIXPBA (MSI-X Pending Bit Array) 0x%08X 0x11068: PBACL (MSI-X PBA Clear) 0x%08X 0x00898: GPIE (General Purpose Interrupt EN) 0x%08X 0x03008: PFCTOP (Priority Flow Ctrl Type Opcode) 0x%08X 0x%05X: FCCTV%d (Flow Ctrl Tx Timer Value %d) 0x%08X 0x%05X: FCRTL%d (Flow Ctrl Rx Threshold low %d) 0x%08X 0x%05X: FCRTH%d (Flow Ctrl Rx Threshold High %d) 0x%08X 0x032A0: FCRTV (Flow Control Refresh Threshold) 0x%08X 0x0CE00: TFCS (Transmit Flow Control Status) 0x%08X 0x%05X: RDBAL%02d (Rx Desc Base Addr Low %02d) 0x%08X 0x%05X: RDBAH%02d (Rx Desc Base Addr High %02d) 0x%08X 0x%05X: RDLEN%02d (Receive Descriptor Length %02d) 0x%08X 0x%05X: RDH%02d (Receive Descriptor Head %02d) 0x%08X 0x%05X: RDT%02d (Receive Descriptor Tail %02d) 0x%08X 0x%05X: RXDCTL%02d (Receive Descriptor Control %02d) 0x%08X 0x%05X: SRRCTL%02d (Split and Replic Rx Control %02d) 0x%08X 0x%05X: DCA_RXCTRL%02d (Rx DCA Control %02d) 0x%08X 0x02F00: RDRXCTL (Receive DMA Control) 0x%08X 0x%05X: RXPBSIZE%d (Receive Packet Buffer Size %d) 0x%08X 0x03000: RXCTRL (Receive Control) 0x%08X 0x03D04: DROPEN (Drop Enable Control) 0x%08X 0x05000: RXCSUM (Receive Checksum Control) 0x%08X 0x05008: RFCTL (Receive Filter Control) 0x%08X 0x%05X: RAL%02d (Receive Address Low%02d) 0x%08X 0x%05X: RAH%02d (Receive Address High %02d) 0x%08X 0x05480: PSRTYPE (Packet Split Receive Type) 0x%08X 0x05090: MCSTCTRL (Multicast Control) 0x%08X 0x05818: MRQC (Multiple Rx Queues Command) 0x%08X 0x0581C: VMD_CTL (VMDq Control) 0x%08X 0x%05X: IMIR%d (Immediate Interrupt Rx %d) 0x%08X 0x%05X: IMIREXT%d (Immed. Interr. Rx Extended %d) 0x%08X 0x05AC0: IMIRVP (Immed. Interr. Rx VLAN Prior.) 0x%08X 0x%05X: TDBAL%02d (Tx Desc Base Addr Low %02d) 0x%08X 0x%05X: TDBAH%02d (Tx Desc Base Addr High %02d) 0x%08X 0x%05X: TDLEN%02d (Tx Descriptor Length %02d) 0x%08X 0x%05X: TDH%02d (Transmit Descriptor Head %02d) 0x%08X 0x%05X: TDT%02d (Transmit Descriptor Tail %02d) 0x%08X 0x%05X: TXDCTL%02d (Tx Descriptor Control %02d) 0x%08X 0x%05X: TDWBAL%02d (Tx Desc Compl. WB Addr low %02d) 0x%08X 0x%05X: TDWBAH%02d (Tx Desc Compl. WB Addr High %02d) 0x%08X 0x07E00: DTXCTL (DMA Tx Control) 0x%08X 0x%05X: DCA_TXCTRL%02d (Tx DCA Control %02d) 0x%08X 0x0CB00: TIPG (Transmit IPG Control) 0x%08X 0x%05X: TXPBSIZE%d (Transmit Packet Buffer Size %d) 0x%08X 0x0CD10: MNGTXMAP (Manageability Tx TC Mapping) 0x%08X 0x05800: WUC (Wake up Control) 0x%08X 0x05808: WUFC (Wake Up Filter Control) 0x%08X 0x05810: WUS (Wake Up Status) 0x%08X 0x05838: IPAV (IP Address Valid) 0x%08X 0x05840: IP4AT (IPv4 Address Table) 0x%08X 0x05880: IP6AT (IPv6 Address Table) 0x%08X 0x05900: WUPL (Wake Up Packet Length) 0x%08X 0x05A00: WUPM (Wake Up Packet Memory) 0x%08X 0x09000: FHFT (Flexible Host Filter Table) 0x%08X 0x07F40: DPMCS (Desc. Plan Music Ctrl Status) 0x%08X 0x0CD00: PDPMCS (Pkt Data Plan Music ctrl Stat) 0x%08X 0x050A0: RUPPBMR (Rx User Prior to Pkt Buff Map) 0x%08X 0x%05X: RT2CR%d (Receive T2 Configure %d) 0x%08X 0x%05X: RT2SR%d (Recieve T2 Status %d) 0x%08X 0x%05X: TDTQ2TCCR%d (Tx Desc TQ2 TC Config %d) 0x%08X 0x%05X: TDTQ2TCSR%d (Tx Desc TQ2 TC Status %d) 0x%08X 0x%05X: TDPT2TCCR%d (Tx Data Plane T2 TC Config %d) 0x%08X 0x%05X: TDPT2TCSR%d (Tx Data Plane T2 TC Status %d) 0x%08X 0x04000: crcerrs (CRC Error Count) 0x%08X 0x04004: illerrc (Illegal Byte Error Count) 0x%08X 0x04008: errbc (Error Byte Count) 0x%08X 0x04010: mspdc (MAC Short Packet Discard Count) 0x%08X 0x%05X: mpc%d (Missed Packets Count %d) 0x%08X 0x04034: mlfc (MAC Local Fault Count) 0x%08X 0x04038: mrfc (MAC Remote Fault Count) 0x%08X 0x04040: rlec (Receive Length Error Count) 0x%08X 0x03F60: lxontxc (Link XON Transmitted Count) 0x%08X 0x0CF60: lxonrxc (Link XON Received Count) 0x%08X 0x03F68: lxofftxc (Link XOFF Transmitted Count) 0x%08X 0x0CF68: lxoffrxc (Link XOFF Received Count) 0x%08X 0x%05X: pxontxc%d (Priority XON Tx Count %d) 0x%08X 0x%05X: pxonrxc%d (Priority XON Received Count %d) 0x%08X 0x%05X: pxofftxc%d (Priority XOFF Tx Count %d) 0x%08X 0x%05X: pxoffrxc%d (Priority XOFF Received Count %d) 0x%08X 0x0405C: prc64 (Packets Received (64B) Count) 0x%08X 0x04060: prc127 (Packets Rx (65-127B) Count) 0x%08X 0x04064: prc255 (Packets Rx (128-255B) Count) 0x%08X 0x04068: prc511 (Packets Rx (256-511B) Count) 0x%08X 0x0406C: prc1023 (Packets Rx (512-1023B) Count) 0x%08X 0x04070: prc1522 (Packets Rx (1024-Max) Count) 0x%08X 0x04074: gprc (Good Packets Received Count) 0x%08X 0x04078: bprc (Broadcast Packets Rx Count) 0x%08X 0x0407C: mprc (Multicast Packets Rx Count) 0x%08X 0x04080: gptc (Good Packets Transmitted Count) 0x%08X 0x04088: gorcl (Good Octets Rx Count Low) 0x%08X 0x0408C: gorch (Good Octets Rx Count High) 0x%08X 0x04090: gotcl (Good Octets Tx Count Low) 0x%08X 0x04094: gotch (Good Octets Tx Count High) 0x%08X 0x%05X: rnbc%d (Receive No Buffers Count %d) 0x%08X 0x040A4: ruc (Receive Undersize count) 0x%08X 0x040A8: rfc (Receive Fragment Count) 0x%08X 0x040AC: roc (Receive Oversize Count) 0x%08X 0x040B0: rjc (Receive Jabber Count) 0x%08X 0x040B4: mngprc (Management Packets Rx Count) 0x%08X 0x040B8: mngpdc (Management Pkts Dropped Count) 0x%08X 0x0CF90: mngptc (Management Packets Tx Count) 0x%08X 0x040C0: torl (Total Octets Rx Count Low) 0x%08X 0x040C4: torh (Total Octets Rx Count High) 0x%08X 0x040D0: tpr (Total Packets Received) 0x%08X 0x040D4: tpt (Total Packets Transmitted) 0x%08X 0x040D8: ptc64 (Packets Tx (64B) Count) 0x%08X 0x040DC: ptc127 (Packets Tx (65-127B) Count) 0x%08X 0x040E0: ptc255 (Packets Tx (128-255B) Count) 0x%08X 0x040E4: ptc511 (Packets Tx (256-511B) Count) 0x%08X 0x040E8: ptc1023 (Packets Tx (512-1023B) Count) 0x%08X 0x040EC: ptc1522 (Packets Tx (1024-Max) Count) 0x%08X 0x040F0: mptc (Multicast Packets Tx Count) 0x%08X 0x040F4: bptc (Broadcast Packets Tx Count) 0x%08X 0x04120: xec (XSUM Error Count) 0x%08X 0x%05X: qprc%02d (Queue Packets Rx Count %02d) 0x%08X 0x%05X: qptc%02d (Queue Packets Tx Count %02d) 0x%08X 0x%05X: qbrc%02d (Queue Bytes Rx Count %02d) 0x%08X 0x%05X: qbtc%02d (Queue Bytes Tx Count %02d) 0x%08X 0x04200: PCS1GCFIG (PCS_1G Gloabal Config 1) 0x%08X 0x04208: PCS1GLCTL (PCS_1G Link Control) 0x%08X 0x0420C: PCS1GLSTA (PCS_1G Link Status) 0x%08X 0x04210: PCS1GDBG0 (PCS_1G Debug 0) 0x%08X 0x04214: PCS1GDBG1 (PCS_1G Debug 1) 0x%08X 0x04218: PCS1GANA (PCS-1G Auto Neg. Adv.) 0x%08X 0x0421C: PCS1GANLP (PCS-1G AN LP Ability) 0x%08X 0x04220: PCS1GANNP (PCS_1G Auto Neg Next Page Tx) 0x%08X 0x04224: PCS1GANLPNP (PCS_1G Auto Neg LPs Next Page) 0x%08X 0x04244: HLREG1 (Highlander Status 1) 0x%08X 0x04248: PAP (Pause and Pace) 0x%08X 0x0424C: MACA (MDI Auto-Scan Command and Addr) 0x%08X 0x04250: APAE (Auto-Scan PHY Address Enable) 0x%08X 0x04254: ARD (Auto-Scan Read Data) 0x%08X 0x04258: AIS (Auto-Scan Interrupt Status) 0x%08X 0x0425C: MSCA (MDI Single Command and Addr) 0x%08X 0x04260: MSRWD (MDI Single Read and Write Data) 0x%08X 0x04264: MLADD (MAC Address Low) 0x%08X 0x04268: MHADD (MAC Addr High/Max Frame size) 0x%08X 0x0426C: TREG (Test Register) 0x%08X 0x04288: PCSS1 (XGXS Status 1) 0x%08X 0x0428C: PCSS2 (XGXS Status 2) 0x%08X 0x04290: XPCSS (10GBASE-X PCS Status) 0x%08X 0x04298: SERDESC (SERDES Interface Control) 0x%08X 0x0429C: MACS (FIFO Status/CNTL Report) 0x%08X 0x042A0: AUTOC (Auto Negotiation Control) 0x%08X 0x042A8: AUTOC2 (Auto Negotiation Control 2) 0x%08X 0x042AC: AUTOC3 (Auto Negotiation Control 3) 0x%08X 0x042B0: ANLP1 (Auto Neg Lnk Part. Ctrl Word 1) 0x%08X 0x042B0: ANLP2 (Auto Neg Lnk Part. Ctrl Word 2) 0x%08X 0x04800: ATLASCTL (Atlas Analog Configuration) 0x%08X 0x02C20: RDSTATCTL (Rx DMA Statistic Control) 0x%08X 0x%05X: RDSTAT%d (Rx DMA Statistics %d) 0x%08X 0x02F08: RDHMPN (Rx Desc Handler Mem Page num) 0x%08X 0x02F10: RIC_DW0 (Rx Desc Hand. Mem Read Data 0) 0x%08X 0x02F14: RIC_DW1 (Rx Desc Hand. Mem Read Data 1) 0x%08X 0x02F18: RIC_DW2 (Rx Desc Hand. Mem Read Data 2) 0x%08X 0x02F1C: RIC_DW3 (Rx Desc Hand. Mem Read Data 3) 0x%08X 0x02F20: RDPROBE (Rx Probe Mode Status) 0x%08X 0x07C20: TDSTATCTL (Tx DMA Statistic Control) 0x%08X 0x%05X: TDSTAT%d (Tx DMA Statistics %d) 0x%08X 0x07F08: TDHMPN (Tx Desc Handler Mem Page Num) 0x%08X 0x07F10: TIC_DW0 (Tx Desc Hand. Mem Read Data 0) 0x%08X 0x07F14: TIC_DW1 (Tx Desc Hand. Mem Read Data 1) 0x%08X 0x07F18: TIC_DW2 (Tx Desc Hand. Mem Read Data 2) 0x%08X 0x07F1C: TIC_DW3 (Tx Desc Hand. Mem Read Data 3) 0x%08X 0x07F20: TDPROBE (Tx Probe Mode Status) 0x%08X 0x0C600: TXBUFCTRL (TX Buffer Access Control) 0x%08X 0x0C610: TXBUFDATA0 (TX Buffer DATA 0) 0x%08X 0x0C614: TXBUFDATA1 (TX Buffer DATA 1) 0x%08X 0x0C618: TXBUFDATA2 (TX Buffer DATA 2) 0x%08X 0x0C61C: TXBUFDATA3 (TX Buffer DATA 3) 0x%08X 0x03600: RXBUFCTRL (RX Buffer Access Control) 0x%08X 0x03610: RXBUFDATA0 (RX Buffer DATA 0) 0x%08X 0x03614: RXBUFDATA1 (RX Buffer DATA 1) 0x%08X 0x03618: RXBUFDATA2 (RX Buffer DATA 2) 0x%08X 0x0361C: RXBUFDATA3 (RX Buffer DATA 3) 0x%08X 0x%05X: PCIE_DIAG%d (PCIe Diagnostic %d) 0x%08X 0x050A4: RFVAL (Receive Filter Validation) 0x%08X 0x042B8: MDFTC1 (MAC DFT Control 1) 0x%08X 0x042C0: MDFTC2 (MAC DFT Control 2) 0x%08X 0x042C4: MDFTFIFO1 (MAC DFT FIFO 1) 0x%08X 0x042C8: MDFTFIFO2 (MAC DFT FIFO 2) 0x%08X 0x042CC: MDFTS (MAC DFT Status) 0x%08X 0x1106C: PCIEECCCTL (PCIe ECC Control) 0x%08X 0x0C300: PBTXECC (Packet Buffer Tx ECC) 0x%08X 0x03300: PBRXECC (Packet Buffer Rx ECC) 0x%08X %s Interrupt: %s ActiveIdleIn ProgressForce10/100AdvertiseHalf/FullNot Not DoneReversedNormalFailedPassedAcceptedRejectedReverseMaskedEnhancedReducedForcedFree-RunningPhase-AdjustedBypassedFailed or Not RunDetectedMac/BIU Registers 0x00: CR (Command): 0x%08x Transmit %s Receive %s Reset In Progress 0x04: CFG (Configuration): 0x%08x %s Endian Boot ROM %s Internal Phy %s Phy Reset %s External Phy %s Default Auto-Negotiation %s, %s %s Mb %s Duplex Phy Interrupt %sAuto-Cleared Phy Configuration = 0x%02x Auto-Negotiation %s %s Polarity %s Duplex %d Mb/s Link %s 0x08: MEAR (EEPROM Access): 0x%08x 0x0c: PTSCR (PCI Test Control): 0x%08x EEPROM Self Test %s Rx Filter Self Test %s Tx FIFO Self Test %s Rx FIFO Self Test %s EEPROM Reload In Progress 0x10: ISR (Interrupt Status): 0x%08x Rx CompleteRx DescriptorRx Packet ErrorRx Early ThresholdRx IdleRx OverrunTx Packet OKTx DescriptorTx Packet ErrorTx IdleTx UnderrunMIB ServiceSoftwarePower Management EventPhyHigh Bits ErrorRx Status FIFO OverrunReceived Target AbortReceived Master AbortSignaled System ErrorDetected Parity ErrorRx Reset CompleteTx Reset Complete No Interrupts Active 0x14: IMR (Interrupt Mask): 0x%08x 0x18: IER (Interrupt Enable): 0x%08x Interrupts %s 0x20: TXDP (Tx Descriptor Pointer): 0x%08x 0x24: TXCFG (Tx Config): 0x%08x Drain Threshhold = %d bytes (%d) Fill Threshhold = %d bytes (%d) Max DMA Burst per Tx = %d bytes Automatic Tx Padding %s Mac Loopback %s Heartbeat Ignore %s Carrier Sense Ignore %s 0x30: RXDP (Rx Descriptor Pointer): 0x%08x 0x34: RXCFG (Rx Config): 0x%08x Drain Threshhold = %d bytes (%d) Max DMA Burst per Rx = %d bytes Long Packets %s Tx Packets %s Runt Packets %s Error Packets %s 0x3c: CCSR (CLKRUN Control/Status): 0x%08x CLKRUNN %s Power Management %s Power Management Event Pending 0x40: WCSR (Wake-on-LAN Control/Status): 0x%08x Wake on Phy Interrupt Enabled Wake on Unicast Packet Enabled Wake on Multicast Packet Enabled Wake on Broadcast Packet Enabled Wake on Arp Enabled Wake on Pattern 0 Match Enabled Wake on Pattern 1 Match Enabled Wake on Pattern 2 Match Enabled Wake on Pattern 3 Match Enabled Wake on Magic Packet Enabled Magic Packet SecureOn Enabled SecureOn Hack Detected Phy Interrupt Received Unicast Packet Received Multicast Packet Received Broadcast Packet Received Arp Received Pattern 0 Received Pattern 1 Received Pattern 2 Received Pattern 3 Received Magic Packet Received 0x44: PCR (Pause Control/Status): 0x%08x Pause Counter = %d Pause %sNegotiated Pause on DA %s Pause on Mulitcast %s Pause %s PS_RCVD: Pause Frame Received 0x48: RFCR (Rx Filter Control): 0x%08x Unicast Hash %s Multicast Hash %s Arp %s Pattern 0 Match %s Pattern 1 Match %s Pattern 2 Match %s Pattern 3 Match %s Perfect Match %s All Unicast %s All Multicast %s All Broadcast %s Rx Filter %s 0x4c: RFDR (Rx Filter Data): 0x%08x PMATCH 1-0 = 0x%08x PMATCH 3-2 = 0x%08x PMATCH 5-4 = 0x%08x PCOUNT 1-0 = 0x%08x PCOUNT 3-2 = 0x%08x SOPASS 1-0 = 0x%08x SOPASS 3-2 = 0x%08x SOPASS 5-4 = 0x%08x 0x50: BRAR (Boot ROM Address): 0x%08x Automatically Increment Address 0x54: BRDR (Boot ROM Data): 0x%08x 0x58: SRR (Silicon Revision): 0x%08x 0x5c: MIBC (Mgmt Info Base Control): 0x%08x Counter Overflow Warning Counters Frozen 0x60: MIB[0] (Rx Errored Packets): 0x%04x Value = %d 0x64: MIB[1] (Rx Frame Sequence Errors): 0x%02x 0x68: MIB[2] (Rx Missed Packets): 0x%02x 0x6c: MIB[3] (Rx Alignment Errors): 0x%02x 0x70: MIB[4] (Rx Symbol Errors): 0x%02x 0x74: MIB[5] (Rx Long Frame Errors): 0x%02x 0x78: MIB[6] (Tx Heartbeat Errors): 0x%02x Internal Phy Registers 0x80: BMCR (Basic Mode Control): 0x%04x %s Duplex Port is Powered %s Auto-Negotiation %s %d Mb/s Auto-Negotiation Restarting Port Isolated Loopback Enabled 0x84: BMSR (Basic Mode Status): 0x%04x Link %s %sCapable of Auto-Negotiation Auto-Negotiation %sComplete %sCapable of Preamble Suppression %sCapable of 10Base-T Half Duplex %sCapable of 10Base-T Full Duplex %sCapable of 100Base-TX Half Duplex %sCapable of 100Base-TX Full Duplex %sCapable of 100Base-T4 Jabber Condition Detected Remote Fault Detected 0x88: PHYIDR1 (PHY ID #1): 0x%04x 0x8c: PHYIDR2 (PHY ID #2): 0x%04x OUI = 0x%06x Model = 0x%02x (%d) Revision = 0x%01x (%d) 0x90: ANAR (Autoneg Advertising): 0x%04x Protocol Selector = 0x%02x (%d) Advertising 10Base-T Half Duplex Advertising 10Base-T Full Duplex Advertising 100Base-TX Half Duplex Advertising 100Base-TX Full Duplex Advertising 100Base-T4 Advertising Pause Indicating Remote Fault Next Page Desired 0x94: ANLPAR (Autoneg Partner): 0x%04x Supports 10Base-T Half Duplex Supports 10Base-T Full Duplex Supports 100Base-TX Half Duplex Supports 100Base-TX Full Duplex Supports 100Base-T4 Supports Pause Indicates Remote Fault Indicates Acknowledgement 0x98: ANER (Autoneg Expansion): 0x%04x Link Partner Can %sAuto-Negotiate Link Code Word %sReceived Next Page %sSupported Link Partner Next Page %sSupported Parallel Detection Fault 0x9c: ANNPTR (Autoneg Next Page Tx): 0x%04x 0xc0: PHYSTS (Phy Status): 0x%04x Link %s %d Mb/s %s Duplex Auto-Negotiation %sComplete %s Polarity MII Interrupt Detected False Carrier Detected Rx Error Detected 0xc4: MICR (MII Interrupt Control): 0x%04x MII Interrupts %s 0xc8: MISR (MII Interrupt Status): 0x%04x Rx Error Counter Half-Full Interrupt %s False Carrier Counter Half-Full Interrupt %s Auto-Negotiation Complete Interrupt %s Remote Fault Interrupt %s Jabber Interrupt %s Link Change Interrupt %s MII Interrupt Pending 0xcc: PGSEL (Phy Register Page Select): 0x%04x 0xd0: FCSCR (False Carrier Counter): 0x%04x 0xd4: RECR (Rx Error Counter): 0x%04x 0xd8: PCSR (100Mb/s PCS Config/Status): 0x%04x NRZI Bypass %s %s Signal Detect Algorithm %s Signal Detect Operation True Quiet Mode %s Rx Clock is %s 4B/5B Operation %s Forced 100 Mb/s Good Link 0xe4: PHYCR (Phy Control): 0x%04x Phy Address = 0x%x (%d) %sPause Compatible with Link Partner LED Stretching %s Phy Self Test %s Self Test Sequence = PSR%d 0xe8: TBTSCR (10Base-T Status/Control): 0x%04x Jabber %s Heartbeat %s Polarity Auto-Sense/Correct %s %s Polarity %s Normal Link Pulse %s 10 Mb/s Loopback %s Forced 10 Mb/s Good Link 'Magic' Phy Registers 0xe4: PMDCSR: 0x%04x 0xf4: DSPCFG: 0x%04x 0xf8: SDCFG: 0x%04x 0xfc: TSTDAT: 0x%04x Magic number 0x%08x does not match 0x%08x Address Data ------- ------ 0x%02x 0x%04x Driver: %s Version: %s APROM: %04x CSR%02d: BCR%02d: MII%02d: CSR0: Status and Control 0x%04x ERR BABL CERR MISS MERR RINT TINT IDON INTR RXON TXON TDMD STOP STRT INIT CSR3: Interrupt Mask 0x%04x BABLM MISSM MERRM RINTM TINTM IDONM DXSUFLO LAPPEN DXMT2PD EMBA BSWP CSR4: Test and Features 0x%04x EN124 DMAPLUS TXDPOLL APAD_XMT ASTRP_RCV MFCO MFCON UINTCMD UINT RCVCCO RCVCCOM TXSTRT TXSTRTM JAB JABM CSR5: Ext Control and Int 1 0x%04x TOKINTD LTINTEN SINT SINTE SLPINT SLPINTE EXDINT EXDINTE MPPLBA MPINT MPINTE MPEN MPMODE SPND CSR7: Ext Control and Int 2 0x%04x FASTSPNDE RXFRTG RDMD RXDPOLL STINT STINTE MREINT MREINTE MAPINT MAPINTE MCCINT MCCINTE MCCIINT MCCIINTE MIIPDTINT MIIPDTINTE CSR15: Mode 0x%04x CSR40: Current RX Byte Count 0x%04x CSR41: Current RX Status 0x%04x CSR42: Current TX Byte Count 0x%04x CSR43: Current TX Status 0x%04x CSR88: Chip ID Lower 0x%04x PCnet/PCI 79C970 PCnet/PCI II 79C970A PCnet/FAST 79C971 PCnet/FAST+ 79C972 PCnet/FAST III 79C973 PCnet/Home 79C978 PCnet/FAST III 79C975 PCnet/PRO 79C976CSR89: Chip ID Upper 0x%04x VER: %04x PARTIDU: %04x CSR112: Missed Frame Count 0x%04x CSR114: RX Collision Count 0x%04x BCR2: Misc. Configuration 0x%04x TMAULOOP LEDPE APROMWE INTLEVEL EADISEL AWAKE ASEL XMAUSEL BCR9: Full-Duplex Control 0x%04x BCR18: Burst and Bus Control 0x%04x BCR19: EEPROM Control and Status 0x%04x PVALID EEDET BCR23: PCI Subsystem Vendor ID 0x%04x BCR24: PCI Subsystem ID 0x%04x BCR31: Software Timer 0x%04x BCR32: MII Control and Status 0x%04x BCR35: PCI Vendor ID 0x%04x SERR TimeOut SWInt TxNoBuf RxFIFO LinkChg RxNoBuf TxErr RxErr RxOK %s%s%s%s%s%s%s%s%s%s%s ERxGood ERxBad ERxOverWrite ERxOK , RESETUnknown RealTek chip (mask: 0x%08x) RealTek %s registers: -------------------------------------------------------- 0x00: MAC Address %02x:%02x:%02x:%02x:%02x:%02x 0x08: Multicast Address Filter 0x%08x 0x%08x 0x10: Dump Tally Counter Command 0x%08x 0x%08x 0x20: Tx Normal Priority Ring Addr 0x%08x 0x%08x 0x28: Tx High Priority Ring Addr 0x%08x 0x%08x 0x10: Transmit Status Desc 0 0x%08x 0x14: Transmit Status Desc 1 0x%08x 0x18: Transmit Status Desc 2 0x%08x 0x1C: Transmit Status Desc 3 0x%08x 0x20: Transmit Start Addr 0 0x%08x 0x24: Transmit Start Addr 1 0x%08x 0x28: Transmit Start Addr 2 0x%08x 0x2C: Transmit Start Addr 3 0x%08x 0x30: Flash memory read/write 0x%08x 0x30: Rx buffer addr (C mode) 0x%08x 0x34: Early Rx Byte Count %8u 0x36: Early Rx Status 0x%02x %s%s%s%s 0x37: Command 0x%02x Rx %s, Tx %s%s 0x38: Current Address of Packet Read (C mode) 0x%04x 0x3A: Current Rx buffer address (C mode) 0x%04x 0x3C: Interrupt Mask 0x%04x 0x3E: Interrupt Status 0x%04x 0x40: Tx Configuration 0x%08x 0x44: Rx Configuration 0x%08x 0x48: Timer count 0x%08x 0x4C: Missed packet counter 0x%06x 0x50: EEPROM Command 0x%02x 0x51: Config 0 0x%02x 0x52: Config 1 0x%02x 0x53: Config 2 0x%02x 0x54: Config 3 0x%02x 0x55: Config 4 0x%02x 0x56: Config 5 0x%02x 0x58: Timer interrupt 0x%08x 0x5C: Multiple Interrupt Select 0x%04x 0x60: PHY access 0x%08x 0x54: Timer interrupt 0x%08x 0x58: Media status 0x%02x 0x59: Config 3 0x%02x 0x5A: Config 4 0x%02x 0x64: TBI control and status 0x%08x 0x68: TBI Autonegotiation advertisement (ANAR) 0x%04x 0x6A: TBI Link partner ability (LPAR) 0x%04x 0x6C: PHY status 0x%02x 0x84: PM wakeup frame 0 0x%08x 0x%08x 0x8C: PM wakeup frame 1 0x%08x 0x%08x 0x94: PM wakeup frame 2 (low) 0x%08x 0x%08x 0x9C: PM wakeup frame 2 (high) 0x%08x 0x%08x 0xA4: PM wakeup frame 3 (low) 0x%08x 0x%08x 0xAC: PM wakeup frame 3 (high) 0x%08x 0x%08x 0xB4: PM wakeup frame 4 (low) 0x%08x 0x%08x 0xBC: PM wakeup frame 4 (high) 0x%08x 0x%08x 0xC4: Wakeup frame 0 CRC 0x%04x 0xC6: Wakeup frame 1 CRC 0x%04x 0xC8: Wakeup frame 2 CRC 0x%04x 0xCA: Wakeup frame 3 CRC 0x%04x 0xCC: Wakeup frame 4 CRC 0x%04x 0xDA: RX packet maximum size 0x%04x 0x78: PHY parameter 1 0x%08x 0x7C: Twister parameter 0x%08x 0x80: PHY parameter 2 0x%02x 0x82: Low addr of a Tx Desc w/ Tx DMA OK 0x%04x 0x82: MII register 0x%02x 0x84: PM CRC for wakeup frame 0 0x%02x 0x85: PM CRC for wakeup frame 1 0x%02x 0x86: PM CRC for wakeup frame 2 0x%02x 0x87: PM CRC for wakeup frame 3 0x%02x 0x88: PM CRC for wakeup frame 4 0x%02x 0x89: PM CRC for wakeup frame 5 0x%02x 0x8A: PM CRC for wakeup frame 6 0x%02x 0x8B: PM CRC for wakeup frame 7 0x%02x 0x8C: PM wakeup frame 0 0x%08x 0x%08x 0x94: PM wakeup frame 1 0x%08x 0x%08x 0x9C: PM wakeup frame 2 0x%08x 0x%08x 0xA4: PM wakeup frame 3 0x%08x 0x%08x 0xAC: PM wakeup frame 4 0x%08x 0x%08x 0xB4: PM wakeup frame 5 0x%08x 0x%08x 0xBC: PM wakeup frame 6 0x%08x 0x%08x 0xC4: PM wakeup frame 7 0x%08x 0x%08x 0xCC: PM LSB CRC for wakeup frame 0 0x%02x 0xCD: PM LSB CRC for wakeup frame 1 0x%02x 0xCE: PM LSB CRC for wakeup frame 2 0x%02x 0xCF: PM LSB CRC for wakeup frame 3 0x%02x 0xD0: PM LSB CRC for wakeup frame 4 0x%02x 0xD1: PM LSB CRC for wakeup frame 5 0x%02x 0xD2: PM LSB CRC for wakeup frame 6 0x%02x 0xD3: PM LSB CRC for wakeup frame 7 0x%02x 0xD4: Flash memory read/write 0x%08x 0xD8: Config 5 0x%02x 0xE0: C+ Command 0x%04x Big-endian mode Home LAN enable VLAN de-tagging RX checksumming PCI 64-bit DAC PCI Multiple RW 0xE2: Interrupt Mitigation 0x%04x TxTimer: %u TxPackets: %u RxTimer: %u RxPackets: %u 0xE4: Rx Ring Addr 0x%08x 0x%08x 0xEC: Early Tx threshold 0x%02x 0xFC: External MII register 0x%08x 0xF0: Func Event 0x%08x 0xF4: Func Event Mask 0x%08x 0xF8: Func Preset State 0x%08x 0xFC: Func Force Event 0x%08x 0x5E: PCI revision id 0x%02x 0x60: Transmit Status of All Desc (C mode) 0x%04x 0x62: MII Basic Mode Control Register 0x%04x 0x64: MII Basic Mode Status Register 0x%04x 0x66: MII Autonegotiation Advertising 0x%04x 0x68: MII Link Partner Ability 0x%04x 0x6A: MII Expansion 0x%04x 0x6C: MII Disconnect counter 0x%04x 0x6E: MII False carrier sense counter 0x%04x 0x70: MII Nway test 0x%04x 0x72: MII RX_ER counter 0x%04x 0x74: MII CS configuration 0x%04x RTL-8139RTL-8139-KRTL-8139ARTL-8139A-GRTL-8139BRTL-8130RTL-8139CRTL-8100RTL-8100B/8139DRTL-8139C+RTL-8101RTL-8169RTL-8169SRTL-8110SRTL-8169/8110SBRTL-8169/8110SCdRTL-8169/8110SCeRTL-8168/8111BbRTL-8168/8111BefRTL-8101EbcRTL-8100E(1)RTL-8100E(2)Address Data ---------- ---- 0x%08x 0x%02x Offset Value ------ ---------- 0x%04x 0x%08x ddee(e@eXepeeeeeeAddr %d %02X%c Init 0x%08X Value 0x%08X Test 0x%02X Control 0x%02X %s End Address 0x%08X Write Pointer 0x%08X Read Pointer 0x%08X Packet Counter 0x%08X Level 0x%08X Control 0x%08X Control/Test 0x%08X %-32s 0x%08X MAC AddressesConnector type 0x%02X (%c) PMD type 0x%02X (%c) PHY type 0x%02X Chip Id 0x%02X GenesisYukonYukon-LiteYukon-LPYukon-2 XLYukon ExtremeYukon-2 EC UltraYukon-2 ECYukon-2 FEYukon-2 FE PlusYukon SupremeYukon Ultra 2Yukon Optima(Unknown) (rev %d) Ram Buffer 0x%02X %12s address: %02X %02XStatus 0x%04X Control 0x%04X Transmit 0x%04X Receive 0x%04X Transmit flow control 0x%04X Transmit parameter 0x%04X Serial mode 0x%04X SourcePhysical PCI config ----------%02x: %02xControl RegistersRegister Access Port 0x%02X LED Control/Status 0x%08X Interrupt Source 0x%08X Interrupt Mask 0x%08X Interrupt Hardware Error Source 0x%08X Interrupt Hardware Error Mask 0x%08X Interrupt Control 0x%08X Interrupt Moderation Mask 0x%08X Hardware Moderation Mask 0x%08X Moderation TimerGeneral Purpose I/O 0x%08X Buffer control 0x%04X Byte Counter %d Descriptor Address 0x%08X%08X Status 0x%08X Timestamp 0x%08X BMU Control/Status 0x%08X Done 0x%04X Request 0x%08X%08X Csum1 Offset %4d Position %d Csum2 Offset %4d Position %d Csum Start 0x%04X Pos %4d Write %d %s (disabled) Descriptor Address 0x%08X%08X Address Counter 0x%08X%08X Current Byte Counter %d Flag & FIFO Address 0x%08X Next 0x%08X Data 0x%08X%08X Start Address 0x%08X Upper Threshold/Pause Packets 0x%08X Lower Threshold/Pause Packets 0x%08X Upper Threshold/High Priority 0x%08X Lower Threshold/High Priority 0x%08X %s Prefetch Control 0x%08X Last Index %u Start Address 0x%08x%08x TX1 report %u TX2 report %u TX threshold %u Put Index %u Get Index %u Bus Management Unit-------------------CSR Receive Queue 1 0x%08X CSR Sync Queue 1 0x%08X CSR Async Queue 1 0x%08X CSR Receive Queue 2 0x%08X CSR Async Queue 2 0x%08X CSR Sync Queue 2 0x%08X GMAC 1TimerBlink SourceReceive Queue 1Sync Transmit Queue 1Async Transmit Queue 1Receive RAMbuffer 1Sync Transmit RAMbuffer 1Async Transmit RAMbuffer 1Receive MAC FIFO 1Transmit MAC FIFO 1Receive Queue 2Async Transmit Queue 2Sync Transmit Queue 2Receive RAMbuffer 2Sync Transmit RAMbuffer 2Async Transmit RAMbuffer 21Receive MAC FIFO 2Transmit MAC FIFO 2Descriptor PollStatusReceive 1Transmit 1Receive 2Transmit 2 Status FIFO Write Pointer 0x%02X Read Pointer 0x%02X Level 0x%02X Watermark 0x%02X ISR Watermark 0x%02X Status levelTX statusISR GMAC control 0x%04X GPHY control 0x%04X LINK control 0x%02hX Rx GMAC 1Tx GMAC 1GMAC 2Rx GMAC 2Tx GMAC 2End AddressAlmost Full ThreshControl/TestFIFO Flush MaskFIFO Flush ThresholdTruncation ThresholdUpper Pause ThresholdLower Pause ThresholdVLAN TagFIFO Write PointerFIFO Write LevelFIFO Read PointerFIFO Read Levelethtool_regs %-20s = %04x %-20s = %04x cmdversion%08x = %08x LAN911x Registers offset 0x50, ID_REV = 0x%08X offset 0x54, INT_CFG = 0x%08X offset 0x58, INT_STS = 0x%08X offset 0x5C, INT_EN = 0x%08X offset 0x60, RESERVED = 0x%08X offset 0x64, BYTE_TEST = 0x%08X offset 0x68, FIFO_INT = 0x%08X offset 0x6C, RX_CFG = 0x%08X offset 0x70, TX_CFG = 0x%08X offset 0x74, HW_CFG = 0x%08X offset 0x78, RX_DP_CTRL = 0x%08X offset 0x7C, RX_FIFO_INF = 0x%08X offset 0x80, TX_FIFO_INF = 0x%08X offset 0x84, PMT_CTRL = 0x%08X offset 0x88, GPIO_CFG = 0x%08X offset 0x8C, GPT_CFG = 0x%08X offset 0x90, GPT_CNT = 0x%08X offset 0x94, FPGA_REV = 0x%08X offset 0x98, ENDIAN = 0x%08X offset 0x9C, FREE_RUN = 0x%08X offset 0xA0, RX_DROP = 0x%08X offset 0xA4, MAC_CSR_CMD = 0x%08X offset 0xA8, MAC_CSR_DATA = 0x%08X offset 0xAC, AFC_CFG = 0x%08X offset 0xB0, E2P_CMD = 0x%08X offset 0xB4, E2P_DATA = 0x%08X index 1, MAC_CR = 0x%08X index 2, ADDRH = 0x%08X index 3, ADDRL = 0x%08X index 4, HASHH = 0x%08X index 5, HASHL = 0x%08X index 6, MII_ACC = 0x%08X index 7, MII_DATA = 0x%08X index 8, FLOW = 0x%08X index 9, VLAN1 = 0x%08X index A, VLAN2 = 0x%08X index B, WUFF = 0x%08X index C, WUCSR = 0x%08X index 0, Basic Control Reg = 0x%04X index 1, Basic Status Reg = 0x%04X index 2, PHY identifier 1 = 0x%04X index 3, PHY identifier 2 = 0x%04X index 4, Auto Negotiation Advertisement Reg = 0x%04X index 5, Auto Negotiation Link Partner Ability Reg = 0x%04X index 6, Auto Negotiation Expansion Register = 0x%04X index 7, Reserved = 0x%04X index 8, Reserved = 0x%04X index 9, Reserved = 0x%04X index 10, Reserved = 0x%04X index 11, Reserved = 0x%04X index 12, Reserved = 0x%04X index 13, Reserved = 0x%04X index 14, Reserved = 0x%04X index 15, Reserved = 0x%04X index 16, Silicon Revision Reg = 0x%04X index 17, Mode Control/Status Reg = 0x%04X index 18, Special Modes = 0x%04X index 19, Reserved = 0x%04X index 20, TSTCNTL = 0x%04X index 21, TSTREAD1 = 0x%04X index 22, TSTREAD2 = 0x%04X index 23, TSTWRITE = 0x%04X index 24, Reserved = 0x%04X index 25, Reserved = 0x%04X index 26, Reserved = 0x%04X index 27, Control/Status Indication = 0x%04X index 28, Special internal testability = 0x%04X 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INT_VEC_DIS_CHARNORM_INT_VEC_DIS_KERDRV_INT_EN_CHARCHAR_INT_KERCHAR_INT_CHARCHAR_INT_LEVE_SELDRV_INT_EN_KERKER_INT_KERKER_INT_CHARKER_INT_LEVE_SELADR_REGION0ADR_REGION1ADR_REGION2ADR_REGION3ST MAC 10/100 Registers control reg 0x%08X addr HI 0x%08X addr LO 0x%08X multicast hash HI 0x%08X multicast hash LO 0x%08X MII addr 0x%08X MII data %08X flow control 0x%08X VLAN1 tag 0x%08X VLAN2 tag 0x%08X mac wakeup frame 0x%08X mac wakeup crtl 0x%08X DMA Registers CSR%d 0x%08X DMA cur tx buf addr 0x%08X DMA cur rx buf addr 0x%08X ST GMAC Registers GMAC Registers Reg%d 0x%08X 4 L< PD@X\ Th V@ B(Dt :4 L< PD@XX0 T@ B(Dt :4 L< PD@XHZP0 TX0 T\ Th V@ B(Dt :  R LX@ B(D Src IP addr: %s mask: %s Dest IP addr: %s mask: %s TOS: 0x%x mask: 0x%x Filter: %d Rule Type: TCP over IPv4 Rule Type: UDP over IPv4 Rule Type: SCTP over IPv4 Src port: %d mask: 0x%x Dest port: %d mask: 0x%x Rule Type: IPSEC AH over IPv4 Rule Type: IPSEC ESP over IPv4 SPI: %d mask: 0x%x Rule Type: Raw IPv4 Protocol: %d mask: 0x%x L4 bytes: 0x%x mask: 0x%x Flow Type: Raw Ethernet Src MAC addr: %02X:%02X:%02X:%02X:%02X:%02X mask: %02X:%02X:%02X:%02X:%02X:%02X Dest MAC addr: %02X:%02X:%02X:%02X:%02X:%02X mask: %02X:%02X:%02X:%02X:%02X:%02X Ethertype: 0x%X mask: 0x%X Unknown Flow type: %d VLAN EtherType: 0x%x mask: 0x%x VLAN: 0x%x mask: 0x%x User-defined: 0x%llx mask: 0x%llx Dest MAC addr: %02X:%02X:%02X:%02X:%02X:%02X mask: %02X:%02X:%02X:%02X:%02X:%02X Action: Direct to queue %llu Action: Drop rxclass: Cannot get RX class ruleIPv6 flows not implemented rxclass: Unknown flow type rxclass: Cannot get RX class rule countrxclass: Cannot allocate memory for RX class rule locationsrxclass: Cannot get RX class rulesTotal %d rules rmgr: Cannot allocate memory for RX class rule locationsrmgr: Cannot get RX class rulesrmgr: Invalid RX class rules table sizermgr: Cannot allocate memory for RX class rulesrmgr: Location out of range rmgr: Cannot find appropriate slot to insert rule rmgr: Cannot insert RX class ruleAdded rule with ID %d rmgr: Cannot delete RX class rule%s-maskAdd rule, unrecognized option[%s] Add rule, invalid syntax Invalid %s value[%s] Invalid %s mask[%s] srcdstprotoactionlocvlan-etypevlanuser-defsrc-ipdst-iptosl4protol4dataspisrc-portdst-portdst-mac %-41s : %-41s : 0x%02xIdentifier (no module present, unknown, or unspecified) (GBIC) (module soldered to motherboard) (SFP) (reserved or unknown)Extended identifier (GBIC not specified / not MOD_DEF compliant) (GBIC/SFP defined by 2-wire interface ID) (GBIC compliant with MOD_DEF %u) (unknown)Connector (unknown or unspecified) (SC) (Fibre Channel Style 1 copper) (Fibre Channel Style 2 copper) (BNC/TNC) (Fibre Channel coaxial headers) (FibreJack) (LC) (MT-RJ) (MU) (SG) (Optical pigtail) (MPO Parallel Optic) (HSSDC II) (Copper pigtail) (RJ45) %-41s : 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x Transceiver codes%s 10G Ethernet: 10G Base-ER [SFF-8472 rev10.4 only] Transceiver type :%s 10G Ethernet: 10G Base-LRM %s 10G Ethernet: 10G Base-LR %s 10G Ethernet: 10G Base-SR %s Infiniband: 1X SX %s Infiniband: 1X LX %s Infiniband: 1X Copper Active %s Infiniband: 1X Copper Passive %s ESCON: ESCON MMF, 1310nm LED %s ESCON: ESCON SMF, 1310nm Laser %s SONET: OC-192, short reach %s SONET: SONET reach specifier bit 1 %s SONET: SONET reach specifier bit 2 %s SONET: OC-48, long reach %s SONET: OC-48, intermediate reach %s SONET: OC-48, short reach %s SONET: OC-12, single mode, long reach %s SONET: OC-12, single mode, inter. reach %s SONET: OC-12, short reach %s SONET: OC-3, single mode, long reach %s SONET: OC-3, single mode, inter. reach %s SONET: OC-3, short reach %s Ethernet: BASE-PX %s Ethernet: BASE-BX10 %s Ethernet: 100BASE-FX %s Ethernet: 100BASE-LX/LX10 %s Ethernet: 1000BASE-T %s Ethernet: 1000BASE-CX %s Ethernet: 1000BASE-LX %s Ethernet: 1000BASE-SX %s FC: very long distance (V) %s FC: short distance (S) %s FC: intermediate distance (I) %s FC: long distance (L) %s FC: medium distance (M) %s FC: Shortwave laser, linear Rx (SA) %s FC: Longwave laser (LC) %s FC: Electrical inter-enclosure (EL) %s FC: Electrical intra-enclosure (EL) %s FC: Shortwave laser w/o OFC (SN) %s FC: Shortwave laser with OFC (SL) %s FC: Longwave laser (LL) %s FC: Copper Active %s FC: Copper Passive %s FC: Copper FC-BaseT %s FC: Twin Axial Pair (TW) %s FC: Twisted Pair (TP) %s FC: Miniature Coax (MI) %s FC: Video Coax (TV) %s FC: Multimode, 62.5um (M6) %s FC: Multimode, 50um (M5) %s FC: Single Mode (SM) %s FC: 1200 MBytes/sec %s FC: 800 MBytes/sec %s FC: 400 MBytes/sec %s FC: 200 MBytes/sec %s FC: 100 MBytes/sec Encoding (unspecified) (8B/10B) (4B/5B) (NRZ) (Manchester) (SONET Scrambled) (64B/66B) %-41s : %u%s BR, NominalMBdRate identifier (4/2/1G Rate_Select & AS0/AS1) (8/4/2G Rx Rate_Select only) (8/4/2G Independent Rx & Tx Rate_Select) (8/4/2G Tx Rate_Select only)Length (SMF,km)kmLength (SMF)Length (50um)Length (62.5um)Length (Copper)Length (OM3)Passive Cu cmplnce. (SFF-8431 appendix E) [SFF-8472 rev10.4 only]Active Cu cmplnce. (SFF-8431 limiting) %-41s : %unm Laser wavelengthVendor name %-41s : %02x:%02x:%02x Vendor OUIVendor PNVendor rev8ppttp4pTtttpp@tt@p 0pLt htqq@uu@Receiver signal OMAReceiver signal average optical powerLaser bias current high alarmOnOff %-41s : No Optical diagnostics support %-41s : Yes %-41s : %.3f mA Laser bias current %-41s : %.4f mW / %.2f dBm Laser output power %-41s : %.2f degrees C / %.2f degrees F Module temperature %-41s : %.4f V Module voltage %-41s : %s Laser bias current high alarm thresholdLaser bias current low alarm thresholdLaser bias current high warning thresholdLaser bias current low warning thresholdLaser output power high alarm thresholdLaser output power low alarm thresholdLaser output power high warning thresholdLaser output power low warning thresholdModule temperature high alarm thresholdModule temperature low alarm thresholdModule temperature high warning thresholdModule temperature low warning thresholdModule voltage high alarm thresholdModule voltage low alarm thresholdModule voltage high warning thresholdModule voltage low warning thresholdLaser rx power high alarm thresholdLaser rx power low alarm thresholdLaser rx power high warning thresholdLaser rx power low warning thresholdAlarm/warning flags implementedLaser bias current low alarmLaser bias current high warningLaser bias current low warningLaser output power high alarmLaser output power low alarmLaser output power high warningLaser output power low warningModule temperature high alarmModule temperature low alarmModule temperature high warningModule temperature low warningModule voltage high alarmModule voltage low alarmModule voltage high warningModule voltage low warningLaser rx power high alarmLaser rx power low alarmLaser rx power high warningLaser rx power low warningT$8\  $ d= (,5`$XT4\2d? \p+<(+0?H)$6|(?<    @? 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