Ð þí #8ô(/¼xlnx,zynq-7000&Zynq Zed Development Boardchosen",console=ttyPS0,115200 earlyprintkaliasesmemory5memoryA pmuarm,cortex-a9-pmuEPAø‰ø‰0amba simple-busPainterrupt-controller@f8f01000arm,cortex-a9-gichyAøðøðŽ”cache-controllerarm,pl310-cacheAøð  œ ­½Ëuart@e0000000 xlnx,xuartps ×disabledÞ(åref_clkaper_clkAà Euart@e0001000 xlnx,xuartps×okayÞ)åref_clkaper_clkAà E2slcr@f8000000xlnx,zynq-slcrAøclocksclkcñxlnx,ps7-clkcþü Ujarmpllddrplliopllcpu_6or4xcpu_3or2xcpu_2xcpu_1xddr2xddr3xdcilqspismcpcapgem0gem1fclk0fclk1fclk2fclk3can0can1sdio0sdio1uart0uart1spi0spi1dmausb0_aperusb1_apergem0_apergem1_apersdio0_apersdio1_aperspi0_aperspi1_apercan0_apercan1_aperi2c0_aperi2c1_aperuart0_aperuart1_apergpio_aperlqspi_apersmc_aperswdtdbg_trcdbg_apbŽ”ttc0@f8001000P$E    cdns,ttcÞAø"ttc1@f8002000P$E%&' cdns,ttcÞAø "scutimer@f8f00600P E arm,cortex-a9-twd-timerAøð Þ #address-cells#size-cellscompatiblemodelbootargsdevice_typereginterruptsinterrupt-parentranges#interrupt-cellsinterrupt-controllerlinux,phandlearm,data-latencyarm,tag-latencycache-unifiedcache-levelstatusclocksclock-names#clock-cellsps-clk-frequencyclock-output-namesclock-ranges