! 8<(VF610 Tower Board!fsl,vf610-twrfsl,vf610chosen,console=ttyLP1,115200aliases'5/soc/aips-bus@40000000/serial@40027000'=/soc/aips-bus@40000000/serial@40028000'E/soc/aips-bus@40000000/serial@40029000'M/soc/aips-bus@40000000/serial@4002a000'U/soc/aips-bus@40080000/serial@400a9000']/soc/aips-bus@40080000/serial@400aa000%e/soc/aips-bus@40000000/gpio@40049000%k/soc/aips-bus@40000000/gpio@4004a000%q/soc/aips-bus@40000000/gpio@4004b000%w/soc/aips-bus@40000000/gpio@4004c000%}/soc/aips-bus@40000000/gpio@4004d000memorymemorycpuscpu@0!arm,cortex-a5cpuclockssxosc !fixed-clockfxosc !fixed-clockn6audio_ext !fixed-clockwenet_ext !fixed-clocksoc !simple-busaips-bus@40000000!fsl,aips-bussimple-bus@interrupt-controller@40002000!arm,cortex-a9-gic@0@!l2-cache@40006000!arm,pl310-cache@`  +serial@40027000!fsl,vf610-lpuart@p ;=F'Mipg Ydisabledserial@40028000!fsl,vf610-lpuart@ ;>F(MipgYokay`defaultnserial@40029000!fsl,vf610-lpuart@ ;?F)Mipg Ydisabledserial@4002a000!fsl,vf610-lpuart@ ;@F*Mipg Ydisabledsai@40031000!fsl,vf610-sai@ ;VFlMsai Ydisabledpit@40037000!fsl,vf610-pit@p ;'F-Mpitwdog@4003e000!fsl,vf610-wdtfsl,imx21-wdt@FLMwdogquadspi@40044000!fsl,vf610-qspi@@ ;Ft} Mqspi_enqspi Ydisablediomuxc@40048000!fsl,vf610-iomuxc@xdcu0dcu0grp_1DxBBBBBBBBBBBBBBBBBBBBBBBBBB BBBdspi0dspi0grp_1Pesdhc1esdhc1grp_181<1@1D1H1L1!fec0fec0grp_10000000000fec1fec1grp_1000000000i2c0i2c0grp_1(<0@0pwm0pwm0grp_1xX\`dptqspi0qspi0grp_1<0{@0D0sH0sL0sP0{X0{\0`0sd0sh0sl0{sai2sai2grp_1p $,d0h4luart1uart1grp_1(h!l|!usbvbususbvbusgrp_1(8!!gpio@40049000!fsl,vf610-gpio@@@ ;k gpio@4004a000!fsl,vf610-gpio@@@@ ;l gpio@4004b000!fsl,vf610-gpio@@@ ;m@ gpio@4004c000!fsl,vf610-gpio@@@ ;n` gpio@4004d000!fsl,vf610-gpio@@@ ;oanatop@40050000!fsl,vf610-anatop@i2c@40066000!fsl,vf610-i2c@` ;GF.Mipg Ydisabledccm@4006b000!fsl,vf610-ccm@aips-bus@40080000!fsl,aips-bussimple-bus@serial@400a9000!fsl,vf610-lpuart@  ;AF+Mipg Ydisabledserial@400aa000!fsl,vf610-lpuart@  ;BF,Mipg Ydisabledethernet@400d0000!fsl,mvf600-fec@  ;NFE MipgahbptpYokayrmii`defaultnethernet@400d1000!fsl,mvf600-fec@  ;OFE MipgahbptpYokayrmii`defaultn #address-cells#size-cellsmodelcompatiblebootargsserial0serial1serial2serial3serial4serial5gpio0gpio1gpio2gpio3gpio4device_typeregnext-level-cacheclock-frequencyinterrupt-parentranges#interrupt-cellsinterrupt-controllerlinux,phandlecache-unifiedcache-levelarm,data-latencyarm,tag-latencyinterruptsclocksclock-namesstatuspinctrl-namespinctrl-0#gpio-range-cellsfsl,pinsgpio-controller#gpio-cellsgpio-ranges#clock-cellsphy-mode