%h8#(#`Altera SOCFPGA VT!altr,socfpga-vtaltr,socfpgachosen,console=ttyS0,57600aliases5/soc/ethernet@ff700000?/soc/ethernet@ff702000I/soc/serial0@ffc02000Q/soc/serial1@ffc03000Y/soc/timer0@ffc08000`/soc/timer1@ffc09000g/soc/timer2@ffd00000n/soc/timer3@ffd01000memoryumemory@cpuscpu@0!arm,cortex-a9ucpucpu@1!arm,cortex-a9ucpuintc@fffed000!arm,cortex-a9-gicsoc !simple-bususocamba !arm,amba-buspdma@ffe01000!arm,pl330arm,primecell  clkmgr@ffd04000 !altr,clk-mgr@clocksosc1 !fixed-clock!f2s_periph_ref_clk !fixed-clock!main_pll!altr,socfpga-pll-clock1@mpuclk!altr,socfpga-perip-clk18Hmainclk!altr,socfpga-perip-clk18Ldbg_base_clk!altr,socfpga-perip-clk18P  main_qspi_clk!altr,socfpga-perip-clk1Tmain_nand_sdmmc_clk!altr,socfpga-perip-clk1Xcfg_s2f_usr0_clk!altr,socfpga-perip-clk1\  periph_pll!altr,socfpga-pll-clock1emac0_clk!altr,socfpga-perip-clk1  emac1_clk!altr,socfpga-perip-clk1  per_qsi_clk!altr,socfpga-perip-clk1per_nand_mmc_clk!altr,socfpga-perip-clk1per_base_clk!altr,socfpga-perip-clk1  s2f_usr1_clk!altr,socfpga-perip-clk1sdram_pll!altr,socfpga-pll-clock1ddr_dqs_clk!altr,socfpga-perip-clk1ddr_2x_dqs_clk!altr,socfpga-perip-clk1ddr_dq_clk!altr,socfpga-perip-clk1s2f_usr2_clk!altr,socfpga-perip-clk1mpu_periph_clk!altr,socfpga-gate-clk18mpu_l2_ram_clk!altr,socfpga-gate-clk18l4_main_clk!altr,socfpga-gate-clk1F`l3_main_clk!altr,socfpga-gate-clk1l3_mp_clk!altr,socfpga-gate-clk1 OdF`l3_sp_clk!altr,socfpga-gate-clk1 Odl4_mp_clk!altr,socfpga-gate-clk1  OdF`l4_sp_clk!altr,socfpga-gate-clk1  OdF`dbg_at_clk!altr,socfpga-gate-clk1  OhF`dbg_clk!altr,socfpga-gate-clk1  OhF`dbg_trace_clk!altr,socfpga-gate-clk1  OlF`dbg_timer_clk!altr,socfpga-gate-clk1 F`cfg_clk!altr,socfpga-gate-clk1 F`s2f_user0_clk!altr,socfpga-gate-clk1 F` emac_0_clk!altr,socfpga-gate-clk1 Femac_1_clk!altr,socfpga-gate-clk1 Fusb_mp_clk!altr,socfpga-gate-clk1 F Ospi_m_clk!altr,socfpga-gate-clk1 F Ocan0_clk!altr,socfpga-gate-clk1 F Ocan1_clk!altr,socfpga-gate-clk1 F O gpio_db_clk!altr,socfpga-gate-clk1 F Os2f_user1_clk!altr,socfpga-gate-clk1Fsdmmc_clk!altr,socfpga-gate-clk 1Fnand_x_clk!altr,socfpga-gate-clk 1F nand_clk!altr,socfpga-gate-clk 1F 8qspi_clk!altr,socfpga-gate-clk 1F ethernet@ff7000000!altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmacp  sWmacirqg1  sstmmacethokaygmiiethernet@ff7020000!altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmacp  xWmacirqg1  sstmmaceth disabledl2-cache@fffef000!arm,pl310-cache &timer@fffec600!arm,cortex-a9-twd-timer  timer0@ffc08000!snps,dw-apb-timer-sp !jtimer1@ffc09000!snps,dw-apb-timer-sp !jtimer2@ffd00000!snps,dw-apb-timer-osc !jtimer3@ffd01000!snps,dw-apb-timer-osc !jserial0@ffc02000!snps,dw-apb-uart  !pserial1@ffc03000!snps,dw-apb-uart0 !prstmgr@ffd05000 !altr,rst-mgrPsysmgr@ffd08000 !altr,sys-mgrЀ@Ѐ #address-cells#size-cellsmodelcompatiblebootargsethernet0ethernet1serial0serial1timer0timer1timer2timer3device_typeregnext-level-cache#interrupt-cellsinterrupt-controllerlinux,phandleinterrupt-parentrangesinterrupts#dma-cells#dma-channels#dma-requests#clock-cellsclock-frequencyclocksfixed-dividerclk-gatediv-reginterrupt-namesmac-addressclock-namesstatusphy-modecache-unifiedcache-levelreg-shiftreg-io-widthcpu1-start-addr