`~8\,(R[,Freescale i.MX6 Quad SABRE Automotive Board!fsl,imx6q-sabreautofsl,imx6qchosenaliases9,/soc/aips-bus@02000000/spba-bus@02000000/serial@02020000'4/soc/aips-bus@02100000/serial@021e8000'.ipgperpwm@02084000 !fsl,imx6q-pwmfsl,imx27-pwm@@ T>.ipgperpwm@02088000 !fsl,imx6q-pwmfsl,imx27-pwm@ U>.ipgperpwm@0208c000 !fsl,imx6q-pwmfsl,imx27-pwm@ V>.ipgperflexcan@02090000 @ nflexcan@02094000 @@ ogpt@02098000!fsl,imx6q-gpt @ 7wx.ipgpergpio@0209c000!fsl,imx6q-gpiofsl,imx35-gpio @BC(gpio@020a0000!fsl,imx6q-gpiofsl,imx35-gpio @DE(gpio@020a4000!fsl,imx6q-gpiofsl,imx35-gpio @@FG(gpio@020a8000!fsl,imx6q-gpiofsl,imx35-gpio @HI(gpio@020ac000!fsl,imx6q-gpiofsl,imx35-gpio @JK(gpio@020b0000!fsl,imx6q-gpiofsl,imx35-gpio @LM(gpio@020b4000!fsl,imx6q-gpiofsl,imx35-gpio @@NO(kpp@020b8000 @ Rwdog@020bc000!fsl,imx6q-wdtfsl,imx21-wdt @ Pwdog@020c0000!fsl,imx6q-wdtfsl,imx21-wdt @ Q ^disabledccm@020c4000!fsl,imx6q-ccm @@WX4anatop@020c8000#!fsl,imx6q-anatopsysconsimple-bus $16regulator-1p1@110!fsl,anatop-regulatorAvdd1p1P 5h 5regulator-3p0@120!fsl,anatop-regulatorAvdd3p0P*h0 ( 3@regulator-2p5@130!fsl,anatop-regulatorAvdd2p5Ph)00)0regulator-vddcore@140!fsl,anatop-regulatorAcpuP h @ p!8  regulator-vddpu@140!fsl,anatop-regulatorAvddpuP h @  p!8  regulator-vddsoc@140!fsl,anatop-regulatorAvddsocP h @ p!8  usbphy@020c9000"!fsl,imx6q-usbphyfsl,imx23-usbphy  ,  usbphy@020ca000"!fsl,imx6q-usbphyfsl,imx23-usbphy  -snvs@020cc000!fsl,sec-v4.0-monsimple-bus  @snvs-rtc-lp@34!fsl,sec-v4.0-mon-rtc-lp4Xepit@020d0000 @ 8epit@020d4000 @@ 9src@020d8000!fsl,imx6q-srcfsl,imx51-src @[`Ogpc@020dc000!fsl,imx6q-gpc @YZiomuxc-gpr@020e0000!fsl,imx6q-iomuxc-gprsyscon8ldb@020e0008!fsl,imx6q-ldbfsl,imx53-ldb\ ^disabled@!"'()*8.di0_plldi1_plldi0_seldi1_seldi2_seldi3_seldi0di1lvds-channel@0 `   ^disabledlvds-channel@1 `   ^disableddcic@020e4000@@ |dcic@020e8000@ }sdma@020ec000!fsl,imx6q-sdmafsl,imx35-sdma@ .ipgahbfimx/sdma/sdma-imx6q.biniomuxc@020e0000!fsl,imx6q-iomuxc@edefaults audmuxaudmux-1`Th\DPdL`audmux-2`tDh8l<p@ecspi1ecspi1grp-1Hecspi1-sabreautoecspi3ecspi3grp-1Hxtpenetenetgrp-1@Xl\p`tdxh|tDpHxL|PTlXH<@enetgrp-2h@Xl\p`tdxh|tDpHxL|PTlXenetgrp-3@Xl\p`tdxh|tDpHxL|PTlXgpmi-nandgpmi-nand-1 i2c1i2c1grp-10@@i2c1grp-20xH@|L@i2c2i2c2grp-10@@i2c3i2c3grp-10@@uart1uart1grp-10PT uart2uart2grp-10 (uart4uart4grp-10 8usbotgusbotggrp-1$pYusbotggrp-2pYusdhc2usdhc2grp-1X@pYT<YThpYL`pYPdpY\DpY pYpYpYpYusdhc2grp-2X@pYT<YThpYL`pYPdpY\DpYusdhc3usdhc3grp-1pYYpYpYpYpYpYpYpYpYusdhc3grp-2pYYpYpYpYpYusdhc4usdhc4grp-1pYYpY pY$ pY(pY,pY0pY4pY8 pYusdhc4grp-2pYYpY pY$ pY(pYweimweim_cs0grp-1 weimnorgrp-1Th`PdL`H\DX@T<P8L4H0D,@(<$8 40,(hoghoggrp0Pd  aips-bus@02100000!fsl,aips-bussimple-buscaam@02100000ijaipstz@0217c000@usb@02184000!fsl,imx6q-usbfsl,imx27-usb@ +   ^disabledusb@02184200!fsl,imx6q-usbfsl,imx27-usbB (  ^disabledusb@02184400!fsl,imx6q-usbfsl,imx27-usbD )  ^disabledusb@02184600!fsl,imx6q-usbfsl,imx27-usbF *  ^disabledusbmisc@02184800!fsl,imx6q-usbmiscH  ethernet@02188000!fsl,imx6q-fec@vwuu .ipgahbptp^okayedefaultsrgmiimlb@0218c000@$5u~usdhc@02190000!fsl,imx6q-usdhc@  .ipgahbper ^disabledusdhc@02194000!fsl,imx6q-usdhc@@  .ipgahbper ^disabledusdhc@02198000!fsl,imx6q-usdhc@  .ipgahbper^okayedefaults   usdhc@0219c000!fsl,imx6q-usdhc@  .ipgahbper ^disabledi2c@021a0000!fsl,imx6q-i2cfsl,imx21-i2c@ $} ^disabledi2c@021a4000!fsl,imx6q-i2cfsl,imx21-i2c@@ %~ ^disabledi2c@021a8000!fsl,imx6q-i2cfsl,imx21-i2c@ & ^disabledromcp@021ac000@mmdc@021b0000!fsl,imx6q-mmdc@mmdc@021b4000@@weim@021b8000!fsl,imx6q-weim@ edefaults ^disablednor@0,0 !cfi-flash b ocotp@021bc000!fsl,imx6q-ocotp@tzasc@021d0000@ ltzasc@021d4000@@ maudmux@021d8000"!fsl,imx6q-audmuxfsl,imx31-audmux@ ^disabledmipi@021dc000@mipi@021e0000@vdoa@021e4000@@ serial@021e8000!fsl,imx6q-uartfsl,imx21-uart@ .ipgper ^disabledserial@021ec000!fsl,imx6q-uartfsl,imx21-uart@ .ipgper ^disabledserial@021f0000!fsl,imx6q-uartfsl,imx21-uart@ .ipgper^okayedefaultsserial@021f4000!fsl,imx6q-uartfsl,imx21-uart@@ .ipgper ^disabledipu@02400000!fsl,imx6q-ipu@@ .busdi0di1  ipu@02800000!fsl,imx6q-ipu@ .busdi0di1  cpuscpu@0!arm,cortex-a9~cpu Otx2 0 ~$l(h).armpll2_pfd2_396msteppll1_swpll1_sys2=Gcpu@1!arm,cortex-a9~cpucpu@2!arm,cortex-a9~cpucpu@3!arm,cortex-a9~cpu #address-cells#size-cellsmodelcompatibleserial0serial1serial2serial3serial4gpio0gpio1gpio2gpio3gpio4gpio5gpio6device_typereg#interrupt-cellsinterrupt-controllerlinux,phandleclock-frequencyinterrupt-parentrangesinterruptsinterrupt-names#dma-cellsdma-channelsclocksreg-namesclock-namesdmasdma-namesfsl,gpmi-dma-channelstatuspinctrl-namespinctrl-0cache-unifiedcache-levelarm,tag-latencyarm,data-latencyfsl,spi-num-chipselectscs-gpiosspi-max-frequencyfsl,fifo-depthfsl,ssi-dma-events#pwm-cellsgpio-controller#gpio-cells#clock-cellsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onanatop-reg-offsetanatop-vol-bit-shiftanatop-vol-bit-widthanatop-min-bit-valanatop-min-voltageanatop-max-voltageanatop-delay-reg-offsetanatop-delay-bit-shiftanatop-delay-bit-width#reset-cellsgprcrtcsfsl,sdma-ram-script-namefsl,pinsfsl,usbphyfsl,usbmisc#index-cellsphy-modebus-widthcd-gpioswp-gpiosbank-widthfsl,weim-cs-timing#crtc-cellsresetsnext-level-cacheoperating-pointsclock-latencyarm-supplypu-supplysoc-supply