R8NX(N  Wandboard i.MX6 Dual Lite Board!!wand,imx6dl-wandboardfsl,imx6dlchosenaliases9,/soc/aips-bus@02000000/spba-bus@02000000/serial@02020000'4/soc/aips-bus@02100000/serial@021e8000'.ipgperpwm@02084000!fsl,imx6q-pwmfsl,imx27-pwm@@ T>.ipgperpwm@02088000!fsl,imx6q-pwmfsl,imx27-pwm@ U>.ipgperpwm@0208c000!fsl,imx6q-pwmfsl,imx27-pwm@ V>.ipgperflexcan@02090000 @ nflexcan@02094000 @@ ogpt@02098000!fsl,imx6q-gpt @ 7wx.ipgpergpio@0209c000!fsl,imx6q-gpiofsl,imx35-gpio @BCgpio@020a0000!fsl,imx6q-gpiofsl,imx35-gpio @DEgpio@020a4000!fsl,imx6q-gpiofsl,imx35-gpio @@FGgpio@020a8000!fsl,imx6q-gpiofsl,imx35-gpio @HIgpio@020ac000!fsl,imx6q-gpiofsl,imx35-gpio @JKgpio@020b0000!fsl,imx6q-gpiofsl,imx35-gpio @LMgpio@020b4000!fsl,imx6q-gpiofsl,imx35-gpio @@NOkpp@020b8000 @ Rwdog@020bc000!fsl,imx6q-wdtfsl,imx21-wdt @ Pwdog@020c0000!fsl,imx6q-wdtfsl,imx21-wdt @ Q ^disabledccm@020c4000!fsl,imx6q-ccm @@WXanatop@020c8000#!fsl,imx6q-anatopsysconsimple-bus $16regulator-1p1@110!fsl,anatop-regulatorvdd1p1 55Mas 5regulator-3p0@120!fsl,anatop-regulatorvdd3p0*50Ma s( 3@regulator-2p5@130!fsl,anatop-regulatorvdd2p55)0Ma0s)0regulator-vddcore@140!fsl,anatop-regulatorcpu 5 Ma@sp  regulator-vddpu@140!fsl,anatop-regulatorvddpu 5 Ma@s p  regulator-vddsoc@140!fsl,anatop-regulatorvddsoc 5 Ma@sp  usbphy@020c9000"!fsl,imx6q-usbphyfsl,imx23-usbphy  ,usbphy@020ca000"!fsl,imx6q-usbphyfsl,imx23-usbphy  -  snvs@020cc000!fsl,sec-v4.0-monsimple-bus  @snvs-rtc-lp@34!fsl,sec-v4.0-mon-rtc-lp4Xepit@020d0000 @ 8epit@020d4000 @@ 9src@020d8000!fsl,imx6q-srcfsl,imx51-src @[`  gpc@020dc000!fsl,imx6q-gpc @YZiomuxc-gpr@020e0000!fsl,imx6q-iomuxc-gprsyscon8ldb@020e0008!fsl,imx6q-ldbfsl,imx53-ldb) ^disabledlvds-channel@0- ^disabledlvds-channel@1- ^disableddcic@020e4000@@ |dcic@020e8000@ }sdma@020ec000!fsl,imx6q-sdmafsl,imx35-sdma@ .ipgahb3imx/sdma/sdma-imx6q.biniomuxc@020e0000!fsl,imx6dl-iomuxc@audmuxaudmux-2`Ltx|ecspi1ecspi1grp-1HLHLDenetenetgrp-1L $( @  enetgrp-2hLH0L4 $(gpmi-nandgpmi-nand-1LpXlTt\x`<$8 lptx|@(i2c1i2c1grp-20Ll@h@uart1uart1grp-10LL`Pduart4uart4grp-10LD,X@ usbotgusbotggrp-2LpYusdhc2usdhc2grp-1LpY 0YpYpYpYpY|pYpYpYpYusdhc3usdhc3grp-1LpY  4YpYpYpY pY$ pY(pY,pY0pYusdhc3grp_2LpY  4YpYpYpY pY  weimweim_cs0grp-1L< weim_norgrp-1L`DHLP T$X(\,`0d4h8l<p@tDxH|LP,($ plhd`\|xtXTpxp@020f0000@ bepdc@020f4000@@ alcdif@020f8000@ 'aips-bus@02100000!fsl,aips-bussimple-buscaam@02100000ijaipstz@0217c000@usb@02184000!fsl,imx6q-usbfsl,imx27-usb@ +U` ^disabledusb@02184200!fsl,imx6q-usbfsl,imx27-usbB (U `^okayusb@02184400!fsl,imx6q-usbfsl,imx27-usbD )` ^disabledusb@02184600!fsl,imx6q-usbfsl,imx27-usbF *` ^disabledusbmisc@02184800l!fsl,imx6q-usbmiscHethernet@02188000!fsl,imx6q-fec@vwuu .ipgahbptp^okaydefault yrgmiimlb@0218c000@$5u~usdhc@02190000!fsl,imx6q-usdhc@  .ipgahbper ^disabledusdhc@02194000!fsl,imx6q-usdhc@@  .ipgahbper ^disabledusdhc@02198000!fsl,imx6q-usdhc@  .ipgahbper^okaydefault usdhc@0219c000!fsl,imx6q-usdhc@  .ipgahbper ^disabledi2c@021a0000!fsl,imx6q-i2cfsl,imx21-i2c@ $} ^disabledi2c@021a4000!fsl,imx6q-i2cfsl,imx21-i2c@@ %~ ^disabledi2c@021a8000!fsl,imx6q-i2cfsl,imx21-i2c@ & ^disabledromcp@021ac000@mmdc@021b0000!fsl,imx6q-mmdc@mmdc@021b4000@@weim@021b8000!fsl,imx6q-weim@ ocotp@021bc000!fsl,imx6q-ocotp@tzasc@021d0000@ ltzasc@021d4000@@ maudmux@021d8000"!fsl,imx6q-audmuxfsl,imx31-audmux@ ^disabledmipi@021dc000@mipi@021e0000@vdoa@021e4000@@ serial@021e8000!fsl,imx6q-uartfsl,imx21-uart@ .ipgper ^disabledserial@021ec000!fsl,imx6q-uartfsl,imx21-uart@ .ipgper ^disabledserial@021f0000!fsl,imx6q-uartfsl,imx21-uart@ .ipgper ^disabledserial@021f4000!fsl,imx6q-uartfsl,imx21-uart@@ .ipgper ^disabledi2c@021f8000 !fsl,imx1-i2c@ # ^disabledipu@02400000!fsl,imx6q-ipu@@ .busdi0di1 cpuscpu@0!arm,cortex-a9~cpu cpu@1!arm,cortex-a9~cpu  #address-cells#size-cellsmodelcompatibleserial0serial1serial2serial3serial4gpio0gpio1gpio2gpio3gpio4gpio5gpio6device_typereg#interrupt-cellsinterrupt-controllerlinux,phandleclock-frequencyinterrupt-parentrangesinterruptsinterrupt-names#dma-cellsdma-channelsclocksreg-namesclock-namesdmasdma-namesfsl,gpmi-dma-channelstatuscache-unifiedcache-levelarm,tag-latencyarm,data-latencypinctrl-namespinctrl-0fsl,fifo-depthfsl,ssi-dma-events#pwm-cellsgpio-controller#gpio-cells#clock-cellsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onanatop-reg-offsetanatop-vol-bit-shiftanatop-vol-bit-widthanatop-min-bit-valanatop-min-voltageanatop-max-voltageanatop-delay-reg-offsetanatop-delay-bit-shiftanatop-delay-bit-width#reset-cellsgprcrtcsfsl,sdma-ram-script-namefsl,pinsfsl,usbphyfsl,usbmisc#index-cellsphy-modebus-width#crtc-cellsresetsnext-level-cache