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À£Žocotp@021bc000!fsl,imx6q-ocotpŠÀ@tzasc@021d0000Š@ êltzasc@021d4000Š@@ êmaudmux@021d8000"!fsl,imx6q-audmuxfsl,imx31-audmuxŠ€@ ^disabledmipi@021dc000ŠÀ@mipi@021e0000Š@vdoa@021e4000Š@@ êserial@021e8000!fsl,imx6q-uartfsl,imx21-uartŠ€@ ê ¡.ipgper ^disabledserial@021ec000!fsl,imx6q-uartfsl,imx21-uartŠÀ@ ê ¡.ipgper ^disabledserial@021f0000!fsl,imx6q-uartfsl,imx21-uartŠ@ ê ¡.ipgper^okayedefaultsserial@021f4000!fsl,imx6q-uartfsl,imx21-uartŠ@@ ê ¡.ipgper ^disabledi2c@021f8000 !fsl,imx1-i2cŠ€@ ê# ^disabledipu@02400000ï!fsl,imx6q-ipuŠ@@ꂃ„ .busdi0di1û´ º cpuscpu@0!arm,cortex-a9~cpuŠcpu@1!arm,cortex-a9~cpuŠ #address-cells#size-cellsmodelcompatibleserial0serial1serial2serial3serial4gpio0gpio1gpio2gpio3gpio4gpio5gpio6device_typereg#interrupt-cellsinterrupt-controllerlinux,phandleclock-frequencyinterrupt-parentrangesinterruptsinterrupt-names#dma-cellsdma-channelsclocksreg-namesclock-namesdmasdma-namesfsl,gpmi-dma-channelstatuspinctrl-namespinctrl-0cache-unifiedcache-levelarm,tag-latencyarm,data-latencyfsl,spi-num-chipselectscs-gpiosspi-max-frequencyfsl,fifo-depthfsl,ssi-dma-events#pwm-cellsgpio-controller#gpio-cells#clock-cellsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onanatop-reg-offsetanatop-vol-bit-shiftanatop-vol-bit-widthanatop-min-bit-valanatop-min-voltageanatop-max-voltageanatop-delay-reg-offsetanatop-delay-bit-shiftanatop-delay-bit-width#reset-cellsgprcrtcsfsl,sdma-ram-script-namefsl,pinsfsl,usbphyfsl,usbmisc#index-cellsphy-modebus-widthcd-gpioswp-gpiosbank-widthfsl,weim-cs-timing#crtc-cellsresetsnext-level-cache