Ð þí  8 `(@ (xlnx,zynq-zc702xlnx,zynq-7000&Zynq ZC702 Development Boardchosen",console=ttyPS1,115200 earlyprintkaliasesmemory5memoryA@amba simple-busEVinterrupt-controller@f8f01000arm,cortex-a9-gic]nAøðøðƒ‰cache-controllerarm,pl310-cacheAøð  ‘ ¢²Àuart@e0000000 xlnx,xuartpsAà Ì×uart@e0001000 xlnx,xuartpsAà Ì2×slcr@f8000000xlnx,zynq-slcrAøclocksps_clkÞ fixed-clockëps_clkþü Rƒ‰armpllÞxlnx,zynq-pll×Aëarmpllƒ‰ddrpllÞxlnx,zynq-pll×Aëddrpllƒ‰iopllÞxlnx,zynq-pll×Aëiopllƒ‰uart_clkÞxlnx,zynq-periph-clock ×ATëuart0_ref_clkuart1_ref_clkƒ‰cpu_clkÞxlnx,zynq-cpu-clock ×A Ä ëcpu_6x4xcpu_3x2xcpu_2xcpu_1xƒ‰ttc0@f8001000 xlnx,ttcAø×cpu_1xttc0.0'okA Ì xlnx,ttc-counter-clocksourcettc0.1'okA Ì xlnx,ttc-counter-clockeventttc0.2 'disabledA Ì ttc1@f8002000. xlnx,ttcAø ×cpu_1xttc1.0 'disabledA Ì%ttc1.1 'disabledA Ì&ttc1.2 'disabledA Ì' #address-cells#size-cellscompatiblemodelbootargsdevice_typereginterrupt-parentranges#interrupt-cellsinterrupt-controllerlinux,phandlearm,data-latencyarm,tag-latencycache-unifiedcache-levelinterruptsclocks#clock-cellsclock-output-namesclock-frequencyclock-namesclock-rangesstatus#interrupt-parent