8 ( HAltera SOCFPGA Cyclone V#!altr,socfpga-cyclone5altr,socfpgachosen,console=ttyS0,57600aliases5/soc/stmmac@ff700000?/soc/serial0@ffc02000G/soc/serial1@ffc03000O/soc/timer0@ffc08000V/soc/timer1@ffc09000]/soc/timer2@ffd00000d/soc/timer3@ffd01000memorykmemoryw@cpuscpu@0!arm,cortex-a9kcpuw{cpu@1!arm,cortex-a9kcpuw{intc@fffed000!arm,cortex-a9-gicwsoc !simple-busksocamba !arm,amba-buspdma@ffe01000!arm,pl330arm,primecellw  stmmac@ff7000000!altr,socfpga-stmmacsnps,dwmac-3.70asnps,dwmacwp  s macirq&gmiil2-cache@fffef000!arm,pl310-cachew &/=timer@fffec600!arm,cortex-a9-twd-timerw  timer0@ffc08000!snps,dw-apb-timer-sp wItimer1@ffc09000!snps,dw-apb-timer-sp wItimer2@ffd00000!snps,dw-apb-timer-osc wI}x@timer3@ffd01000!snps,dw-apb-timer-osc wI}x@serial0@ffc02000!snps,dw-apb-uartw  YcIserial1@ffc03000!snps,dw-apb-uartw0 YcIrstmgr@ffd05000 !altr,rst-mgrwPsysmgr@ffd08000 !altr,sys-mgrwЀ@pЀ #address-cells#size-cellsmodelcompatiblebootargsethernet0serial0serial1timer0timer1timer2timer3device_typeregnext-level-cache#interrupt-cellsinterrupt-controllerlinux,phandleinterrupt-parentrangesinterrupts#dma-cells#dma-channels#dma-requestsinterrupt-namesmac-addressphy-modecache-unifiedcache-levelclock-frequencyreg-shiftreg-io-widthcpu1-start-addr