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00010 #ifndef __SIS3801_INCLUDE__
00011 #define __SIS3801_INCLUDE__
00012
00013 #
00014 #include <stdio.h>
00015 #include <string.h>
00016 #include "mvmestd.h"
00017
00018 #include "stdio.h"
00019 #include "string.h"
00020
00021 #ifdef __cplusplus
00022 extern "C" {
00023 #endif
00024
00025 #ifndef MIDAS_TYPE_DEFINED
00026 #define MIDAS_TYPE_DEFINED
00027
00028 #ifdef __alpha
00029 typedef unsigned int DWORD;
00030 #else
00031 typedef unsigned long int DWORD;
00032 #endif
00033
00034 #endif
00035
00036
00037 #define HALF_FIFO 16384
00038
00039 #define MAX_FIFO_SIZE 2*HALF_FIFO
00040 #define SIS_FIFO_SIZE 4*HALF_FIFO
00041 #define CSR_READ 0x0
00042 #define CSR_FULL 0xffffffff
00043 #define CSR_WRITE 0x0
00044
00045 #define IS_LED 0x00000001
00046 #define LED_ON 0x00000001
00047 #define LED_OFF 0x00000100
00048 #define GET_MODE 0x0000000C
00049 #define MODE_0 0x00000C00
00050 #define MODE_1 0x00000804
00051 #define MODE_2 0x00000408
00052 #define MODE_3 0x0000000C
00053 #define IS_25MHZ 0x00000010
00054 #define ENABLE_25MHZ 0x00000010
00055 #define DISABLE_25MHZ 0x00001000
00056 #define IS_TEST 0x00000020
00057 #define ENABLE_TEST 0x00000020
00058 #define DISABLE_TEST 0x00002000
00059
00060 #define IS_102LNE 0x00000040
00061 #define ENABLE_102LNE 0x00000040
00062 #define DISABLE_102LNE 0x00000400
00063 #define IS_LNE 0x00000080
00064 #define ENABLE_LNE 0x00000080
00065 #define DISABLE_LNE 0x00000800
00066 #define IS_FIFO_EMPTY 0x00000100
00067 #define IS_FIFO_ALMOST_EMPTY 0x00000200
00068 #define IS_FIFO_HALF_FULL 0x00000400
00069 #define IS_FIFO_FULL 0x00001000
00070 #define IS_REF1 0x00002000
00071
00072 #define IS_NEXT_LOGIC_ENABLE 0x00008000
00073 #define IS_EXTERN_NEXT 0x00010000
00074 #define IS_EXTERN_CLEAR 0x00020000
00075 #define IS_EXTERN_DISABLE 0x00040000
00076 #define IS_SOFT_COUNTING 0x00080000
00077 #define ENABLE_EXTERN_NEXT 0x00010000
00078 #define ENABLE_EXTERN_CLEAR 0x00020000
00079 #define ENABLE_EXTERN_DISABLE 0x00040000
00080 #define SET_SOFT_DISABLE 0x00080000
00081 #define DISABLE_EXTERN_NEXT 0x01000000
00082 #define DISABLE_EXTERN_CLEAR 0x02000000
00083 #define DISABLE_EXTERN_DISABLE 0x04000000
00084 #define CLEAR_SOFT_DISABLE 0x08000000
00085
00086 #define IS_IRQ_EN_CIP 0x00100000
00087 #define IS_IRQ_EN_FULL 0x00200000
00088 #define IS_IRQ_EN_HFULL 0x00400000
00089 #define IS_IRQ_EN_ALFULL 0x00800000
00090 #define IS_IRQ_CIP 0x10000000
00091 #define IS_IRQ_FULL 0x20000000
00092 #define IS_IRQ_HFULL 0x40000000
00093 #define IS_IRQ_ALFULL 0x80000000
00094 #define ENABLE_IRQ_CIP 0x00100000
00095 #define ENABLE_IRQ_FULL 0x00200000
00096 #define ENABLE_IRQ_HFULL 0x00400000
00097 #define ENABLE_IRQ_ALFULL 0x00800000
00098 #define DISABLE_IRQ_CIP 0x10000000
00099 #define DISABLE_IRQ_FULL 0x20000000
00100 #define DISABLE_IRQ_HFULL 0x40000000
00101 #define DISABLE_IRQ_ALFULL 0x80000000
00102 #define VME_IRQ_ENABLE 0x00000800
00103
00104 #define SIS3801_CSR_RW 0x000
00105 #define SIS3801_MODULE_ID_RO 0x004
00106 #define SIS3801_IRQ_REG_RW 0x004
00107 #define SIS3801_COPY_REG_WO 0x00C
00108 #define SIS3801_FIFO_WRITE_WO 0x010
00109 #define SIS3801_FIFO_CLEAR_WO 0x020
00110 #define SIS3801_VME_NEXT_CLK_WO 0x024
00111 #define SIS3801_ENABLE_NEXT_CLK_WO 0x028
00112 #define SIS3801_DISABLE_NEXT_CLK_WO 0x02C
00113 #define SIS3801_ENABLE_REF_CH1_WO 0x050
00114 #define SIS3801_DISABLE_REF_CH1_WO 0x054
00115 #define SIS3801_MODULE_RESET_WO 0x060
00116 #define SIS3801_SINGLE_TST_PULSE_WO 0x068
00117 #define SIS3801_PRESCALE_REG_RW 0x080
00118 #define SIS3801_FIFO_RO 0x100 // 0x100..0x1FC
00119
00120 #define SOURCE_CIP 0
00121 #define SOURCE_FIFO_FULL 1
00122 #define SOURCE_FIFO_HFULL 2
00123 #define SOURCE_FIFO_ALFULL 3
00124
00125 #define SIS3801_VECT_BASE 0x7f
00126
00127 DWORD sis3801_module_ID(MVME_INTERFACE *myvme, DWORD base);
00128 void sis3801_module_reset(MVME_INTERFACE *myvme, DWORD base);
00129 DWORD sis3801_IRQ_REG_read(MVME_INTERFACE *myvme, DWORD base);
00130 DWORD sis3801_IRQ_REG_write(MVME_INTERFACE *myvme, DWORD base, DWORD irq);
00131 DWORD sis3801_module_mode(MVME_INTERFACE *myvme, DWORD base, DWORD mode);
00132 DWORD sis3801_dwell_time(MVME_INTERFACE *myvme, DWORD base, DWORD dwell);
00133 int sis3801_ref1(MVME_INTERFACE *myvme, DWORD base, DWORD endis);
00134 int sis3801_next_logic(MVME_INTERFACE *myvme, DWORD base, DWORD endis);
00135 void sis3801_channel_enable(MVME_INTERFACE *myvme, DWORD base, DWORD nch);
00136 DWORD sis3801_CSR_read(MVME_INTERFACE *myvme, DWORD base, const DWORD what);
00137 DWORD sis3801_CSR_write(MVME_INTERFACE *myvme, DWORD base, const DWORD what);
00138 void sis3801_FIFO_clear(MVME_INTERFACE *myvme, DWORD base);
00139 int sis3801_HFIFO_read(MVME_INTERFACE *myvme, DWORD base, DWORD *p);
00140 int sis3801_FIFO_flush(MVME_INTERFACE *myvme, DWORD base, DWORD *p);
00141 void sis3801_int_source (MVME_INTERFACE *myvme, DWORD base, DWORD int_source);
00142 void sis3801_int_source_enable (MVME_INTERFACE *myvme, DWORD base, const int intnum);
00143 void sis3801_int_source_disable (MVME_INTERFACE *myvme, DWORD base, const int intnum);
00144 void sis3801_int_clear (MVME_INTERFACE *myvme, DWORD base, const int intnum);
00145 void sis3801_int_attach (MVME_INTERFACE *myvme, DWORD base, DWORD base_vect, int level, void (*isr)(void));
00146 void sis3801_int_detach (MVME_INTERFACE *myvme, DWORD baser, DWORD base_vect, int level);
00147 void sis3801_setup(const MVME_INTERFACE *myvme, DWORD base, int mode, int dsp);
00148
00149 int sis3801_Setup(MVME_INTERFACE *myvme, DWORD base, int mode);
00150 void sis3801_Status(MVME_INTERFACE *myvme, DWORD base);
00151
00152 #ifdef __cplusplus
00153 }
00154 #endif
00155
00156 #endif // _INCLUDE
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