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00018
00019 #include "sis3803.h"
00020
00021 void myStub_sis3803(void)
00022 {
00023 static int sis3803_private_counter = 0;
00024 #ifdef OS_VXWORKS
00025 sis3803_int_source_disable(0, 0);
00026 logMsg("sis3803 IRQ#%i served\n", sis3803_private_counter++, 0, 0, 0, 0, 0);
00027 sis3803_int_source_enable(0, 0);
00028 #endif
00029 }
00030
00031
00032 INLINE DWORD sis3803_module_ID(const DWORD base_adr)
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043 {
00044 volatile DWORD *spec_adr;
00045
00046 spec_adr = (DWORD *) (A32D24 + base_adr + MODULE_ID);
00047 return *spec_adr;
00048 }
00049
00050
00051 INLINE void sis3803_module_reset(const DWORD base_adr)
00052
00053
00054
00055
00056
00057
00058
00059
00060
00061 {
00062 volatile DWORD *spec_adr;
00063
00064 spec_adr = (DWORD *) (A32D24 + base_adr + MODULE_RESET);
00065 *spec_adr = 0x0;
00066 }
00067
00068
00069 INLINE DWORD sis3803_IRQ_REG_read(const DWORD base_adr)
00070
00071
00072
00073
00074
00075
00076
00077
00078
00079
00080 {
00081 volatile DWORD *spec_adr;
00082
00083 spec_adr = (DWORD *) (A32D24 + base_adr + IRQ_REG);
00084 return (*spec_adr & 0xFFF);
00085 }
00086
00087
00088 INLINE DWORD sis3803_IRQ_REG_write(const DWORD base_adr, DWORD irq)
00089
00090
00091
00092
00093
00094
00095
00096
00097
00098
00099 {
00100 volatile DWORD *spec_adr;
00101
00102 spec_adr = (DWORD *) (A32D24 + base_adr + IRQ_REG);
00103 *spec_adr = irq;
00104 return (*spec_adr & 0xFFF);
00105 }
00106
00107
00108 INLINE DWORD sis3803_input_mode(const DWORD base_adr, DWORD mode)
00109
00110
00111
00112
00113
00114
00115
00116
00117
00118
00119 {
00120 volatile DWORD *spec_adr;
00121
00122 spec_adr = (DWORD *) (A32D24 + base_adr + CSR_WRITE);
00123 if (mode < 4)
00124 mode <<= 2;
00125 *spec_adr = mode;
00126 spec_adr = (DWORD *) (A32D24 + base_adr + CSR_READ);
00127 return ((*spec_adr & GET_MODE) >> 2);
00128 }
00129
00130
00131 INLINE DWORD sis3803_ref1(const DWORD base_adr, DWORD endis)
00132
00133
00134
00135
00136
00137
00138
00139
00140
00141
00142
00143 {
00144 volatile DWORD *spec_adr;
00145
00146 if ((endis == ENABLE_REF_CH1) || (endis == DISABLE_REF_CH1)) {
00147 spec_adr = (DWORD *) (A32D24 + base_adr + endis);
00148 *spec_adr = 0x0;
00149 } else
00150 printf("sis3803_ref1: unknown command %d\n", endis);
00151
00152
00153 spec_adr = (DWORD *) (A32D24 + base_adr + CSR_READ);
00154 return ((*spec_adr & IS_REF1) ? 1 : 0);
00155 }
00156
00157
00158 INLINE void sis3803_channel_enable(const DWORD base_adr, DWORD pat)
00159
00160
00161
00162
00163
00164
00165
00166
00167
00168
00169
00170 {
00171 volatile DWORD *spec_adr;
00172
00173 spec_adr = (DWORD *) (A32D24 + base_adr + SELECT_COUNT_DIS_REG);
00174 *spec_adr = (~pat & 0xffff);
00175 }
00176
00177
00178
00179 INLINE void sis3803_channel_disable(const DWORD base_adr, DWORD pat)
00180
00181
00182
00183
00184
00185
00186
00187
00188
00189
00190
00191 {
00192 volatile DWORD *spec_adr;
00193
00194 spec_adr = (DWORD *) (A32D24 + base_adr + SELECT_COUNT_DIS_REG);
00195 *spec_adr = pat & 0xffff;
00196 }
00197
00198
00199 INLINE DWORD sis3803_CSR_read(const DWORD base_adr, const DWORD what)
00200
00201
00202
00203
00204
00205
00206
00207
00208
00209
00210
00211 {
00212 volatile DWORD *spec_adr;
00213
00214 spec_adr = (DWORD *) (A32D24 + base_adr + CSR_READ);
00215 if (what == CSR_FULL)
00216 return *spec_adr;
00217 else
00218 return ((*spec_adr & what) ? 1 : 0);
00219 }
00220
00221
00222 INLINE DWORD sis3803_CSR_write(const DWORD base_adr, const DWORD what)
00223
00224
00225
00226
00227
00228
00229
00230
00231
00232
00233 {
00234 volatile DWORD *spec_adr;
00235
00236 spec_adr = (DWORD *) (A32D24 + base_adr + CSR_WRITE);
00237 *spec_adr = what;
00238 return sis3803_CSR_read(base_adr, CSR_FULL);
00239 }
00240
00241
00242 INLINE void sis3803_all_clear(const DWORD base_adr)
00243
00244
00245
00246
00247
00248
00249
00250
00251
00252 {
00253 volatile DWORD *spec_adr;
00254
00255 spec_adr = (DWORD *) (A32D24 + base_adr + ALL_CLEAR);
00256 *spec_adr = 0x0;
00257 }
00258
00259
00260 INLINE void sis3803_test_enable(const DWORD base_adr)
00261
00262
00263
00264
00265
00266
00267
00268
00269
00270 {
00271 volatile DWORD *spec_adr;
00272
00273 spec_adr = (DWORD *) (A32D24 + base_adr + CSR_WRITE);
00274 *spec_adr = ENABLE_TEST_PULSE;
00275 }
00276
00277
00278 INLINE void sis3803_test_disable(const DWORD base_adr)
00279
00280
00281
00282
00283
00284
00285
00286
00287
00288 {
00289 volatile DWORD *spec_adr;
00290
00291 spec_adr = (DWORD *) (A32D24 + base_adr + CSR_WRITE);
00292 *spec_adr = DISABLE_TEST_PULSE;
00293 }
00294
00295
00296 INLINE void sis3803_all_enable(const DWORD base_adr)
00297
00298
00299
00300
00301
00302
00303
00304
00305
00306 {
00307 volatile DWORD *spec_adr;
00308
00309 spec_adr = (DWORD *) (A32D24 + base_adr + ENABLE_GBL_COUNT);
00310 *spec_adr = 0x0;
00311 }
00312
00313
00314 INLINE void sis3803_all_disable(const DWORD base_adr)
00315
00316
00317
00318
00319
00320
00321
00322
00323
00324 {
00325 volatile DWORD *spec_adr;
00326
00327 spec_adr = (DWORD *) (A32D24 + base_adr + DISABLE_GBL_COUNT);
00328 *spec_adr = 0x0;
00329 }
00330
00331
00332 INLINE void sis3803_grp1_clear(const DWORD base_adr)
00333
00334
00335
00336
00337
00338
00339
00340
00341
00342 {
00343 volatile DWORD *spec_adr;
00344
00345 spec_adr = (DWORD *) (A32D24 + base_adr + COUNTER_GRP1_CLEAR);
00346 *spec_adr = 0x0;
00347 }
00348
00349
00350 INLINE void sis3803_grp2_clear(const DWORD base_adr)
00351
00352
00353
00354
00355
00356
00357
00358
00359
00360 {
00361 volatile DWORD *spec_adr;
00362
00363 spec_adr = (DWORD *) (A32D24 + base_adr + COUNTER_GRP2_CLEAR);
00364 *spec_adr = 0x0;
00365 }
00366
00367
00368 INLINE void sis3803_single_clear(const DWORD base_adr, const INT ch)
00369
00370
00371
00372
00373
00374
00375
00376
00377
00378 {
00379 volatile DWORD *spec_adr;
00380
00381 if (ch < 16) {
00382 spec_adr = (DWORD *) (A32D24 + base_adr + COUNTER_CLEAR + (ch << 2));
00383 *spec_adr = 0x0;
00384 }
00385 }
00386
00387
00388 INLINE void sis3803_single_OVFL_clear(const DWORD base_adr, INT ch)
00389
00390
00391
00392
00393
00394
00395
00396
00397
00398 {
00399 volatile DWORD *spec_adr;
00400
00401 if (ch < 16) {
00402 spec_adr = (DWORD *) (A32D24 + base_adr + OVERFLOW_CLEAR + (ch << 2));
00403 *spec_adr = 0x0;
00404 }
00405 }
00406
00407
00408 INLINE void sis3803_counter_read(const DWORD base_adr, INT ch, DWORD * pvalue)
00409
00410
00411
00412
00413
00414
00415
00416
00417
00418
00419
00420 {
00421 volatile DWORD *spec_adr;
00422
00423 if (ch < 16) {
00424 spec_adr = (DWORD *) (A32D24 + base_adr + COUNTER_READ + (ch << 2));
00425 *pvalue = *spec_adr;
00426 }
00427 }
00428
00429
00430 INLINE void sis3803_all_read(const DWORD base_adr, DWORD * pvalue)
00431
00432
00433
00434
00435
00436
00437
00438
00439
00440
00441 {
00442 INT i;
00443 volatile DWORD *spec_adr;
00444
00445 spec_adr = (DWORD *) (A32D24 + base_adr + COUNTER_READ);
00446 for (i = 0; i < 16; i++) {
00447 *pvalue++ = *spec_adr++;
00448 }
00449 }
00450
00451
00452 INLINE void sis3803_grp1_read(const DWORD base_adr, DWORD * pvalue)
00453
00454
00455
00456
00457
00458
00459
00460
00461
00462
00463 {
00464 INT i;
00465 volatile DWORD *spec_adr;
00466
00467 spec_adr = (DWORD *) (A32D24 + base_adr + COUNTER_READ);
00468 for (i = 0; i < 8; i++) {
00469 *pvalue++ = *spec_adr++;
00470 }
00471 }
00472
00473
00474 INLINE void sis3803_grp2_read(const DWORD base_adr, DWORD * pvalue)
00475
00476
00477
00478
00479
00480
00481
00482
00483
00484
00485 {
00486 INT i;
00487 volatile DWORD *spec_adr;
00488
00489 spec_adr = (DWORD *) (A32D24 + base_adr + COUNTER_GRP2_READ);
00490 for (i = 0; i < 8; i++) {
00491 *pvalue++ = *spec_adr++;
00492 }
00493 }
00494
00495
00496 INLINE void sis3803_all_read_clear(const DWORD base_adr, DWORD * pvalue)
00497
00498
00499
00500
00501
00502
00503
00504
00505
00506
00507 {
00508 INT i;
00509 volatile DWORD *spec_adr;
00510
00511 spec_adr = (DWORD *) (A32D24 + base_adr + COUNTER_READ_CLEAR);
00512 for (i = 0; i < 16; i++) {
00513 *pvalue++ = *spec_adr++;
00514 }
00515 }
00516
00517
00518 INLINE void sis3803_OVFL_grp1_read(const DWORD base_adr, DWORD * reg)
00519
00520
00521
00522
00523
00524
00525
00526
00527
00528 {
00529 volatile DWORD *spec_adr;
00530
00531 spec_adr = (DWORD *) (A32D24 + base_adr + OVERFLOW_REG1_8);
00532 *reg = *spec_adr;
00533 *reg >>= 24;
00534 }
00535
00536
00537 INLINE void sis3803_OVFL_grp2_read(const DWORD base_adr, DWORD * reg)
00538
00539
00540
00541
00542
00543
00544
00545
00546
00547 {
00548 volatile DWORD *spec_adr;
00549
00550 spec_adr = (DWORD *) (A32D24 + base_adr + OVERFLOW_REG9_16);
00551 *reg = *spec_adr;
00552 *reg >>= 24;
00553 }
00554
00555
00556 INLINE void sis3803_int_source_enable(const DWORD base_adr, const int intnum)
00557
00558
00559
00560
00561
00562
00563
00564
00565
00566
00567
00568 {
00569 volatile DWORD *spec_adr;
00570 DWORD int_source;
00571
00572 spec_adr = (DWORD *) (A32D24 + base_adr + CSR_WRITE);
00573 switch (intnum) {
00574 case 0:
00575 int_source = ENABLE_IRQ_EN_BS0;
00576 break;
00577 case 1:
00578 int_source = ENABLE_IRQ_EN_BS1;
00579 break;
00580 case 2:
00581 int_source = ENABLE_IRQ_EN_BS2;
00582 break;
00583 default:
00584 logMsg("Unknown interrupt source (%d)\n", int_source, 0, 0, 0, 0, 0);
00585 }
00586 *spec_adr = int_source;
00587 }
00588
00589
00590 INLINE void sis3803_int_source_disable(const DWORD base_adr, const int intnum)
00591
00592
00593
00594
00595
00596
00597
00598
00599
00600
00601
00602
00603 {
00604 volatile DWORD *spec_adr;
00605 DWORD int_source;
00606
00607 spec_adr = (DWORD *) (A32D24 + base_adr + CSR_WRITE);
00608 switch (intnum) {
00609 case 0:
00610 int_source = DISABLE_IRQ_DI_BS0;
00611 break;
00612 case 1:
00613 int_source = DISABLE_IRQ_DI_BS1;
00614 break;
00615 case 2:
00616 int_source = DISABLE_IRQ_DI_BS2;
00617 break;
00618 default:
00619 logMsg("Unknown interrupt source (%d)\n", int_source, 0, 0, 0, 0, 0);
00620 }
00621 *spec_adr = int_source;
00622 }
00623
00624
00625 INLINE void sis3803_int_source(const DWORD base_adr, DWORD int_source)
00626
00627
00628
00629
00630
00631
00632
00633
00634
00635
00636
00637 {
00638 volatile DWORD *spec_adr;
00639
00640 spec_adr = (DWORD *) (A32D24 + base_adr + CSR_WRITE);
00641
00642 int_source &= (ENABLE_IRQ_EN_BS0 | ENABLE_IRQ_EN_BS1
00643 | ENABLE_IRQ_EN_BS2
00644 | DISABLE_IRQ_DI_BS0 | DISABLE_IRQ_DI_BS1 | DISABLE_IRQ_DI_BS2);
00645 *spec_adr = int_source;
00646 }
00647
00648
00649 INLINE void sis3803_int_attach(const DWORD base_adr, DWORD base_vect, int level,
00650 void (*isr) (void))
00651
00652
00653
00654
00655
00656
00657
00658
00659
00660
00661
00662
00663
00664 {
00665 volatile DWORD *spec_adr;
00666
00667
00668
00669
00670
00671
00672
00673
00674
00675 #ifdef OS_VXWORKS
00676 if ((level < 8) && (level > 0) && (base_vect < 0x100)) {
00677 spec_adr = (DWORD *) (A32D24 + base_adr + IRQ_REG);
00678 *spec_adr = (level << 8) | VME_IRQ_ENABLE | base_vect;
00679 sysIntEnable(level);
00680 }
00681 intConnect(INUM_TO_IVEC(base_vect), (VOIDFUNCPTR) isr, 0);
00682 #else
00683 printf("Not implemented for this OS\n");
00684 #endif
00685 }
00686
00687
00688 INLINE void sis3803_int_detach(const DWORD base_adr, DWORD base_vect, int level)
00689
00690
00691
00692
00693
00694
00695
00696
00697
00698
00699
00700
00701 {
00702
00703
00704
00705
00706
00707
00708
00709
00710 #ifdef OS_VXWORKS
00711
00712
00713
00714
00715 intConnect(INUM_TO_IVEC(base_vect), (VOIDFUNCPTR) myStub_sis3803, 0);
00716 sysIntDisable(level);
00717 #else
00718 printf("vector : 0x%x\n", base_vect + intnum);
00719 #endif
00720 }
00721
00722
00723 INLINE void sis3803_int_clear(const DWORD base_adr, const int intnum)
00724
00725
00726
00727
00728
00729
00730
00731
00732
00733
00734
00735 {
00736 volatile DWORD *spec_adr;
00737 DWORD int_source;
00738
00739 spec_adr = (DWORD *) (A32D24 + base_adr + CSR_WRITE);
00740 switch (intnum) {
00741 case 0:
00742 int_source = DISABLE_IRQ_DI_BS0;
00743 *spec_adr = int_source;
00744 int_source = ENABLE_IRQ_EN_BS0;
00745 *spec_adr = int_source;
00746 break;
00747 case 1:
00748 int_source = DISABLE_IRQ_DI_BS1;
00749 *spec_adr = int_source;
00750 int_source = ENABLE_IRQ_EN_BS1;
00751 *spec_adr = int_source;
00752 break;
00753 case 2:
00754 int_source = DISABLE_IRQ_DI_BS2;
00755 *spec_adr = int_source;
00756 int_source = ENABLE_IRQ_EN_BS2;
00757 *spec_adr = int_source;
00758 break;
00759 default:
00760 logMsg("Unknown interrupt source (%d)\n", int_source, 0, 0, 0, 0, 0);
00761 }
00762 }
00763
00764
00765 void sis3803_setup(const DWORD base_adr, int mode, int dsp)
00766 {
00767 switch (mode) {
00768 case 1:
00769
00770 if (dsp) {
00771 printf("Setting : %d \t", mode);
00772 printf("Info : PAA/June 2000\n");
00773 }
00774 sis3803_module_reset(base_adr);
00775 sis3803_input_mode(base_adr, 1);
00776 sis3803_all_enable(base_adr);
00777 sis3803_channel_enable(base_adr, 0xf);
00778 if (dsp)
00779 SIS3803_CSR_read(base_adr);
00780 if (dsp)
00781 printf("# of active ch. : 4\n");
00782 break;
00783 default:
00784 printf("Undefined mode %d (known mode :1, 2, 3, 4, 5)\n", mode);
00785 break;
00786 }
00787 }
00788
00789
00790 void sis3803(void)
00791
00792
00793
00794
00795
00796
00797
00798
00799
00800 {
00801 printf("\n---> SIS 3803 32 MultiScalers (sis3803.c) <---\n");
00802 printf("Inline : sis3803_module_ID (vmeBase);\n");
00803 printf("Inline : sis3803_IRQ_REG_read(vmeBase);\n");
00804 printf("Inline : sis3803_IRQ_REG_write(vmeBase, irq);\n");
00805 printf("Inline : sis3803_module_reset (vmeBase);\n");
00806 printf("Inline : sis3803_ref1 (vmeBase, enable/disable);\n");
00807 printf("Inline : sis3803_channel_enable (vmeBase, pattern);\n");
00808 printf("Inline : sis3803_channel_disable (vmeBase, pattern);\n");
00809 printf("Inline : sis3803_CSR_read (vmeBase, what);\n");
00810 printf("Inline : sis3803_CSR_write (vmeBase, what);\n");
00811 printf("Inline : sis3803_test_enable(vmeBase);\n");
00812 printf("Inline : sis3803_test_disable(vmeBase);\n");
00813 printf("Inline : sis3803_all_clear(vmeBase);\n");
00814 printf("Inline : sis3803_all_enable(vmeBase);\n");
00815 printf("Inline : sis3803_all_disable(vmeBase);\n");
00816 printf("Inline : sis3803_grp1_clear(vmeBase);\n");
00817 printf("Inline : sis3803_grp2_clear(vmeBase);\n");
00818 printf("Inline : sis3803_single_clear(vmeBase, ch);\n");
00819 printf("Inline : sis3803_single_OVFL_clear(vmeBase, ch);\n");
00820 printf("Inline : sis3803_counter_read(vmeBase, ch, *p);\n");
00821 printf("Inline : sis3803_all_read(vmeBase, *p);\n");
00822 printf("Inline : sis3803_grp1_read(vmeBase, *p);\n");
00823 printf("Inline : sis3803_grp2_read(vmeBase, *p);\n");
00824 printf("Inline : sis3803_all_read_clear(vmeBase, *p);\n");
00825 printf("Inline : sis3803_OVFL_grp1_read(vmeBase, *p);\n");
00826 printf("Inline : sis3803_OVFL_grp2_read(vmeBase, *p);\n");
00827 printf("Inline : sis3803_int_source (vmeBase, enable/disable);\n");
00828 printf("Inline : sis3803_int_source_enable (vmeBase, source (0..3));\n");
00829 printf("Inline : sis3803_int_source_disable (vmeBase, source (0..3));\n");
00830 printf("Inline : sis3803_int_attach (vmeBase, vect, level, void (*isr)(void));\n");
00831 printf("Inline : sis3803_int_detach (vmeBase, vect, level);\n");
00832 printf("Inline : sis3803_int_clear (vmeBase, source (0..3));\n");
00833 printf(" sis3803_setup(vmeBase, mode, display);\n");
00834 printf("calls : SIS3803_setup( base_adr, mode)\n");
00835 printf("calls : SIS3803_CSR_read( base_adr)\n");
00836 printf("calls : SIS3803_all_read( base_adr) 'sis3803_counter_read()'\n");
00837 printf("calls : SIS3803_all_read_clear( base_adr) 'sis3803_single_clear'\n");
00838 printf("calls : SIS3803_all_bread( base_adr) 'sis3803_all_read'\n");
00839 printf("calls : SIS3803_all_bcread( base_adr) 'sis3803_all_read_clear'\n");
00840 }
00841
00842
00843 void SIS3803_setup(const DWORD base_adr, int mode)
00844 {
00845 sis3803_setup(base_adr, mode, 1);
00846 }
00847
00848 void SIS3803_CSR_read(const DWORD base_adr)
00849 {
00850 DWORD csr;
00851
00852 csr = sis3803_CSR_read(base_adr, CSR_FULL);
00853
00854 printf("Module Version : %d\t", ((sis3803_module_ID(base_adr) & 0xf000) >> 12));
00855 printf("Module ID : %4.4x\n", (sis3803_module_ID(base_adr) >> 16));
00856 printf("LED : %s \t", (csr & IS_LED) ? "Y" : "N");
00857 printf("Input mode : %d \n", sis3803_input_mode(base_adr, 1));
00858 printf("Reference pulse 1: %s \t", (csr & IS_REF1) ? "Y" : "N");
00859 printf("Global Enable : %s \t", (csr & IS_GBL_ENABLE) ? "Y" : "N");
00860 printf("Global OVFL bit : %s \n", (csr & IS_GBL_OVFL) ? "Y" : "N");
00861 printf("IRQ enable BS0 : %s \t", (csr & IS_IRQ_EN_BS0) ? "Y" : "N");
00862 printf("IRQ enable BS1 : %s \t", (csr & IS_IRQ_EN_BS1) ? "Y" : "N");
00863 printf("IRQ enable BS2 : %s \n", (csr & IS_IRQ_EN_BS2) ? "Y" : "N");
00864 printf("IRQ Bit Source 0 : %s \t", (csr & IS_IRQ_BS0) ? "Y" : "N");
00865 printf("IRQ Bit Source 1 : %s \t", (csr & IS_IRQ_BS1) ? "Y" : "N");
00866 printf("IRQ Bit Source 2 : %s \n", (csr & IS_IRQ_BS2) ? "Y" : "N");
00867 printf("internal VME IRQ : %s \t", (csr & 0x4000000) ? "Y" : "N");
00868 printf("VME IRQ : %s \n", (csr & 0x8000000) ? "Y" : "N");
00869 }
00870
00871 void SIS3803_all_read(const DWORD base_adr)
00872 {
00873 DWORD count;
00874 INT i;
00875
00876 for (i = 0; i < 16; i++) {
00877 sis3803_counter_read(base_adr, i, &count);
00878 printf("Counter[%i] : %u\n", i, count);
00879 }
00880 }
00881
00882 void SIS3803_all_read_clear(const DWORD base_adr)
00883 {
00884 DWORD count;
00885 INT i;
00886
00887 for (i = 0; i < 16; i++) {
00888 sis3803_counter_read(base_adr, i, &count);
00889 sis3803_single_clear(base_adr, i);
00890 printf("Counter[%i] : %u\n", i, count);
00891 }
00892 }
00893
00894 void SIS3803_all_bread(const DWORD base_adr)
00895 {
00896 DWORD count[16];
00897 INT i;
00898
00899 sis3803_all_read(base_adr, &(count[0]));
00900 for (i = 0; i < 16; i++) {
00901 printf("Counter[%i] : %u 0x%x\n", i, count[i], count[i]);
00902 }
00903 }
00904
00905 void SIS3803_all_bcread(const DWORD base_adr)
00906 {
00907 DWORD count[16];
00908 INT i;
00909
00910 sis3803_all_read_clear(base_adr, &(count[0]));
00911 for (i = 0; i < 16; i++) {
00912 printf("Counter[%i] : %u\n", i, count[i]);
00913 }
00914 }
00915
00916 DWORD *p = NULL;
00917
00918 void test(DWORD mem)
00919 {
00920 PART_ID part_id;
00921
00922 if (p != NULL)
00923 free(p);
00924 (char *) p = malloc(mem);
00925 }