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00014 #include <stdio.h>
00015 #include <string.h>
00016 #if defined(OS_LINUX)
00017 #include <unistd.h>
00018 #endif
00019
00020
00021 #ifdef MAIN_ENABLE
00022
00023 #include "vmicvme.h"
00024 extern INT_INFO int_info;
00025 int myinfo = VME_INTERRUPT_SIGEVENT;
00026 #endif
00027
00028 #include "sis3801.h"
00029
00030
00031
00032
00033
00034
00035
00036
00037 DWORD sis3801_module_ID(MVME_INTERFACE *mvme, DWORD base)
00038 {
00039 int cmode;
00040 DWORD id;
00041
00042 mvme_get_dmode(mvme, &cmode);
00043 mvme_set_dmode(mvme, MVME_DMODE_D32);
00044 id = mvme_read_value(mvme, base + SIS3801_MODULE_ID_RO);
00045 mvme_set_dmode(mvme, cmode);
00046 return (id);
00047 }
00048
00049
00050
00051
00052 void sis3801_module_reset(MVME_INTERFACE *mvme, DWORD base)
00053 {
00054 int cmode;
00055
00056 mvme_get_dmode(mvme, &cmode);
00057 mvme_set_dmode(mvme, MVME_DMODE_D32);
00058
00059 mvme_write_value(mvme, base + SIS3801_MODULE_RESET_WO, 0x0);
00060 mvme_set_dmode(mvme, cmode);
00061 return;
00062 }
00063
00064
00065
00066
00067
00068 DWORD sis3801_IRQ_REG_read(MVME_INTERFACE *mvme, DWORD base)
00069 {
00070 int cmode, id;
00071 DWORD reg;
00072
00073 mvme_get_dmode(mvme, &cmode);
00074 mvme_set_dmode(mvme, MVME_DMODE_D32);
00075 id = mvme_read_value(mvme, base + SIS3801_IRQ_REG_RW);
00076 mvme_set_dmode(mvme, cmode);
00077 return (reg & 0xFFF);
00078 }
00079
00080
00081
00082
00083
00084
00085
00086 DWORD sis3801_IRQ_REG_write(MVME_INTERFACE *mvme, DWORD base, DWORD vector)
00087 {
00088 int cmode;
00089 DWORD reg;
00090
00091 mvme_get_dmode(mvme, &cmode);
00092 mvme_set_dmode(mvme, MVME_DMODE_D32);
00093
00094 mvme_write_value(mvme, base + SIS3801_IRQ_REG_RW, (vector & 0xFF));
00095 reg = mvme_read_value(mvme, base + SIS3801_IRQ_REG_RW);
00096 mvme_set_dmode(mvme, cmode);
00097 return (reg & 0xFFF);
00098 }
00099
00100
00101
00102
00103
00104
00105
00106 DWORD sis3801_input_mode(MVME_INTERFACE *mvme, DWORD base, DWORD mode)
00107 {
00108 int cmode;
00109 DWORD rmode;
00110
00111 mvme_get_dmode(mvme, &cmode);
00112 mvme_set_dmode(mvme, MVME_DMODE_D32);
00113
00114 if (mode < 4)
00115 mode <<= 2;
00116 mvme_write_value(mvme, base + SIS3801_CSR_RW, mode);
00117
00118 rmode = mvme_read_value(mvme, base + SIS3801_CSR_RW);
00119 mvme_set_dmode(mvme, cmode);
00120 return ((rmode & GET_MODE) >> 2);
00121 }
00122
00123
00124
00125
00126
00127
00128 DWORD sis3801_dwell_time(MVME_INTERFACE *mvme, DWORD base, DWORD dwell)
00129 {
00130 int cmode;
00131 DWORD prescale;
00132
00133 mvme_get_dmode(mvme, &cmode);
00134 mvme_set_dmode(mvme, MVME_DMODE_D32);
00135
00136 prescale = (10 * dwell ) - 1;
00137 if ((prescale > 0) && (prescale < 2<<24))
00138 mvme_write_value(mvme, base + SIS3801_PRESCALE_REG_RW, prescale);
00139
00140 prescale = mvme_read_value(mvme, base + SIS3801_PRESCALE_REG_RW);
00141 mvme_set_dmode(mvme, cmode);
00142
00143 return (prescale);
00144 }
00145
00146
00147
00148
00149
00150
00151
00152 int sis3801_ref1(MVME_INTERFACE *mvme, DWORD base, DWORD endis)
00153 {
00154 int cmode;
00155 DWORD csr;
00156
00157 mvme_get_dmode(mvme, &cmode);
00158 mvme_set_dmode(mvme, MVME_DMODE_D32);
00159
00160 if ((endis == SIS3801_ENABLE_REF_CH1_WO) || (endis == SIS3801_DISABLE_REF_CH1_WO))
00161 {
00162 mvme_write_value(mvme, base + endis, 0x0);
00163 }
00164 else
00165 printf("sis3801_ref1: unknown command %d\n",endis);
00166
00167
00168 csr = mvme_read_value(mvme, base + SIS3801_CSR_RW);
00169 mvme_set_dmode(mvme, cmode);
00170
00171 return ((csr & IS_REF1) ? 1 : 0);
00172
00173 }
00174
00175
00176
00177
00178 int sis3801_next_logic(MVME_INTERFACE *mvme, DWORD base, DWORD endis)
00179 {
00180 int cmode;
00181 DWORD csr;
00182
00183 mvme_get_dmode(mvme, &cmode);
00184 mvme_set_dmode(mvme, MVME_DMODE_D32);
00185
00186 if ((endis == SIS3801_ENABLE_NEXT_CLK_WO) || (endis == SIS3801_DISABLE_NEXT_CLK_WO))
00187 {
00188 mvme_write_value(mvme, base + endis, 0x0);
00189 }
00190 else
00191 printf("sis3801_next_logic: unknown command %d\n",endis);
00192
00193
00194 csr = mvme_read_value(mvme, base + SIS3801_CSR_RW);
00195 mvme_set_dmode(mvme, cmode);
00196
00197 return ((csr & IS_NEXT_LOGIC_ENABLE) ? 1 : 0);
00198 }
00199
00200
00201
00202
00203
00204
00205 void sis3801_channel_enable(MVME_INTERFACE *mvme, DWORD base, DWORD nch)
00206 {
00207 int cmode;
00208
00209 mvme_get_dmode(mvme, &cmode);
00210 mvme_set_dmode(mvme, MVME_DMODE_D32);
00211
00212 if (nch > 24) nch = 32;
00213 mvme_write_value(mvme, base + SIS3801_COPY_REG_WO, (1<<nch));
00214 mvme_set_dmode(mvme, cmode);
00215
00216 return;
00217 }
00218
00219
00220
00221
00222
00223
00224 DWORD sis3801_CSR_read(MVME_INTERFACE *mvme, DWORD base, const DWORD what)
00225 {
00226 int cmode;
00227 DWORD csr;
00228
00229 mvme_get_dmode(mvme, &cmode);
00230 mvme_set_dmode(mvme, MVME_DMODE_D32);
00231
00232 if (what == CSR_FULL)
00233 {
00234 csr = mvme_read_value(mvme, base + SIS3801_CSR_RW);
00235 } else if (what == GET_MODE) {
00236 csr = mvme_read_value(mvme, base + SIS3801_CSR_RW);
00237 csr = ((csr & what) >> 2);
00238 } else {
00239 csr = mvme_read_value(mvme, base + SIS3801_CSR_RW);
00240 csr = ((csr & what) ? 1 : 0);
00241 }
00242 mvme_set_dmode(mvme, cmode);
00243 return (csr);
00244 }
00245
00246
00247
00248
00249
00250 DWORD sis3801_CSR_write(MVME_INTERFACE *mvme, DWORD base, const DWORD what)
00251 {
00252 int cmode;
00253 int csr;
00254
00255 mvme_get_dmode(mvme, &cmode);
00256 mvme_set_dmode(mvme, MVME_DMODE_D32);
00257
00258 mvme_write_value(mvme, base + SIS3801_CSR_RW, what);
00259
00260 csr = sis3801_CSR_read(mvme, base, CSR_FULL);
00261
00262 mvme_set_dmode(mvme, cmode);
00263 return (csr);
00264 }
00265
00266
00267
00268
00269
00270 void sis3801_FIFO_clear(MVME_INTERFACE *mvme, DWORD base)
00271 {
00272 int cmode;
00273
00274 mvme_get_dmode(mvme, &cmode);
00275 mvme_set_dmode(mvme, MVME_DMODE_D32);
00276
00277 mvme_write_value(mvme, base + SIS3801_FIFO_CLEAR_WO, 0x0);
00278
00279 mvme_set_dmode(mvme, cmode);
00280 return;
00281 }
00282
00283
00284
00285
00286
00287
00288
00289
00290
00291 int sis3801_HFIFO_read(MVME_INTERFACE *mvme, DWORD base, DWORD * pfifo)
00292 {
00293 int i, cmode;
00294
00295 mvme_get_dmode(mvme, &cmode);
00296 mvme_set_dmode(mvme, MVME_DMODE_D32);
00297
00298 if (sis3801_CSR_read(mvme, base, IS_FIFO_FULL)) {
00299 mvme_set_dmode(mvme, cmode);
00300 return -1;
00301 }
00302 if (sis3801_CSR_read(mvme, base, IS_FIFO_HALF_FULL) == 0) {
00303 mvme_set_dmode(mvme, cmode);
00304 return 0;
00305 }
00306 for (i=0;i<HALF_FIFO;i++)
00307 *pfifo++ = mvme_read_value(mvme, base + SIS3801_FIFO_RO);
00308
00309 mvme_set_dmode(mvme, cmode);
00310 return HALF_FIFO;
00311 }
00312
00313
00314
00315
00316
00317
00318
00319
00320
00321
00322
00323 int sis3801_FIFO_flush(MVME_INTERFACE *mvme, DWORD base, DWORD * pfifo)
00324 {
00325 int cmode, counter=0;
00326
00327 mvme_get_dmode(mvme, &cmode);
00328 mvme_set_dmode(mvme, MVME_DMODE_D32);
00329
00330 if (sis3801_CSR_read(mvme, base, IS_FIFO_FULL)) {
00331 mvme_set_dmode(mvme, cmode);
00332 return -1;
00333 }
00334 while ((sis3801_CSR_read(mvme, base, IS_FIFO_EMPTY) == 0) && (counter < MAX_FIFO_SIZE))
00335 {
00336 counter++;
00337 *pfifo++ = mvme_read_value(mvme, base + SIS3801_FIFO_RO);
00338 }
00339
00340 mvme_set_dmode(mvme, cmode);
00341 return counter;
00342 }
00343
00344
00345
00346
00347
00348
00349 void sis3801_int_source_enable (MVME_INTERFACE *mvme, DWORD base, const int intnum)
00350 {
00351 int cmode;
00352 DWORD int_source;
00353
00354 mvme_get_dmode(mvme, &cmode);
00355 mvme_set_dmode(mvme, MVME_DMODE_D32);
00356
00357 switch (intnum)
00358 {
00359 case 0:
00360 int_source = ENABLE_IRQ_CIP;
00361 break;
00362 case 1:
00363 int_source = ENABLE_IRQ_FULL;
00364 break;
00365 case 2:
00366 int_source = ENABLE_IRQ_HFULL;
00367 break;
00368 case 3:
00369 int_source = ENABLE_IRQ_ALFULL;
00370 break;
00371 default:
00372 printf("Unknown interrupt source (%d)\n",int_source);
00373 }
00374 mvme_write_value(mvme, base + SIS3801_CSR_RW, int_source);
00375
00376 mvme_set_dmode(mvme, cmode);
00377 return;
00378 }
00379
00380
00381
00382
00383
00384
00385 void sis3801_int_source_disable (MVME_INTERFACE *mvme, DWORD base, const int intnum)
00386 {
00387 int cmode;
00388 DWORD int_source;
00389
00390 mvme_get_dmode(mvme, &cmode);
00391 mvme_set_dmode(mvme, MVME_DMODE_D32);
00392
00393 switch (intnum)
00394 {
00395 case 0:
00396 int_source = DISABLE_IRQ_CIP;
00397 break;
00398 case 1:
00399 int_source = DISABLE_IRQ_FULL;
00400 break;
00401 case 2:
00402 int_source = DISABLE_IRQ_HFULL;
00403 break;
00404 case 3:
00405 int_source = DISABLE_IRQ_ALFULL;
00406 break;
00407 default:
00408 printf("Unknown interrupt source (%d)\n",int_source);
00409 }
00410 mvme_write_value(mvme, base + SIS3801_CSR_RW, int_source);
00411
00412 mvme_set_dmode(mvme, cmode);
00413 return;
00414 }
00415
00416
00417
00418
00419
00420
00421
00422 void sis3801_int_source (MVME_INTERFACE *mvme, DWORD base, DWORD int_source)
00423 {
00424 int cmode;
00425
00426 mvme_get_dmode(mvme, &cmode);
00427 mvme_set_dmode(mvme, MVME_DMODE_D32);
00428
00429 int_source &= (ENABLE_IRQ_CIP | ENABLE_IRQ_FULL
00430 | ENABLE_IRQ_HFULL | ENABLE_IRQ_ALFULL
00431 | DISABLE_IRQ_CIP | DISABLE_IRQ_FULL
00432 | DISABLE_IRQ_HFULL| DISABLE_IRQ_ALFULL);
00433 mvme_write_value(mvme, base + SIS3801_CSR_RW, int_source);
00434
00435 mvme_set_dmode(mvme, cmode);
00436 }
00437
00438
00439
00440
00441
00442
00443
00444
00445
00446
00447
00448 void sis3801_int_attach (MVME_INTERFACE *mvme, DWORD base, DWORD base_vect, int level, void (*isr)(void))
00449 {
00450 int cmode;
00451
00452 mvme_get_dmode(mvme, &cmode);
00453 mvme_set_dmode(mvme, MVME_DMODE_D32);
00454
00455
00456 sis3801_int_source(mvme, base
00457 , DISABLE_IRQ_CIP | DISABLE_IRQ_FULL
00458 | DISABLE_IRQ_HFULL | DISABLE_IRQ_ALFULL);
00459 if ((level < 8) && (level > 0) && (base_vect < 0x100)) {
00460 mvme_write_value(mvme, base + SIS3801_IRQ_REG_RW, (level << 8) | VME_IRQ_ENABLE | base_vect);
00461 mvme_interrupt_attach(mvme, level, base_vect, (void *)isr, &myinfo);
00462 }
00463 mvme_set_dmode(mvme, cmode);
00464 }
00465
00466
00467
00468
00469
00470
00471
00472
00473
00474
00475 void sis3801_int_detach (MVME_INTERFACE *mvme, DWORD base, DWORD base_vect, int level)
00476 {
00477
00478
00479 sis3801_int_source(mvme, base , DISABLE_IRQ_CIP
00480 | DISABLE_IRQ_FULL | DISABLE_IRQ_HFULL
00481 | DISABLE_IRQ_ALFULL);
00482
00483 return;
00484 }
00485
00486
00487
00488
00489
00490
00491
00492
00493
00494 void sis3801_int_clear (MVME_INTERFACE *mvme, DWORD base, const int intnum)
00495 {
00496 DWORD int_source;
00497
00498 switch (intnum)
00499 {
00500 case 0:
00501 int_source = DISABLE_IRQ_CIP;
00502 mvme_write_value(mvme, base + SIS3801_CSR_RW, int_source);
00503 int_source = ENABLE_IRQ_CIP;
00504 mvme_write_value(mvme, base + SIS3801_CSR_RW, int_source);
00505 break;
00506 case 1:
00507 int_source = DISABLE_IRQ_FULL;
00508 mvme_write_value(mvme, base + SIS3801_CSR_RW, int_source);
00509 int_source = ENABLE_IRQ_FULL;
00510 mvme_write_value(mvme, base + SIS3801_CSR_RW, int_source);
00511 break;
00512 case 2:
00513 int_source = DISABLE_IRQ_HFULL;
00514 mvme_write_value(mvme, base + SIS3801_CSR_RW, int_source);
00515 int_source = ENABLE_IRQ_HFULL;
00516 mvme_write_value(mvme, base + SIS3801_CSR_RW, int_source);
00517 break;
00518 case 3:
00519 int_source = DISABLE_IRQ_ALFULL;
00520 mvme_write_value(mvme, base + SIS3801_CSR_RW, int_source);
00521 int_source = ENABLE_IRQ_ALFULL;
00522 mvme_write_value(mvme, base + SIS3801_CSR_RW, int_source);
00523 break;
00524 default:
00525 printf("Unknown interrupt source (%d)\n",int_source);
00526 }
00527
00528 return;
00529 }
00530
00531
00532
00533
00534
00535
00536
00537
00538
00539
00540
00541
00542
00543
00544 int sis3801_Setup(MVME_INTERFACE *mvme, DWORD base, int mode)
00545 {
00546 int cmode;
00547
00548 mvme_get_dmode(mvme, &cmode);
00549 mvme_set_dmode(mvme, MVME_DMODE_D32);
00550
00551 switch (mode) {
00552 case 0x1:
00553 printf("Default setting after power up (mode:%d)\n", mode);
00554 printf("...\n");
00555 printf("...\n");
00556 break;
00557 case 0x2:
00558 break;
00559 default:
00560 printf("Unknown setup mode\n");
00561 mvme_set_dmode(mvme, cmode);
00562 return -1;
00563 }
00564
00565 mvme_set_dmode(mvme, cmode);
00566 return 0;
00567 }
00568
00569
00570
00571
00572 void sis3801_Status(MVME_INTERFACE *mvme, DWORD base)
00573 {
00574 DWORD csr;
00575
00576 csr = sis3801_CSR_read(mvme, base, CSR_FULL);
00577
00578 printf("Module Version : %d\t", ((sis3801_module_ID (mvme, base) & 0xf000) >> 12));
00579 printf("Module ID : %4.4x\t", (sis3801_module_ID (mvme, base) >> 16));
00580 printf("CSR contents : 0x%8.8x\n", csr);
00581 printf("LED : %s \t",(csr & IS_LED) ? "Y" : "N");
00582 printf("FIFO test mode : %s \t",(csr & 0x2) ? "Y" : "N");
00583 printf("Input mode : %d \n",sis3801_input_mode(mvme, base, 2));
00584 printf("25MHz test pulse : %s \t",(csr & IS_25MHZ) ? "Y" : "N");
00585 printf("Input test mode : %s \t",(csr & IS_TEST) ? "Y" : "N");
00586 printf("10MHz to LNE : %s \t",(csr & IS_102LNE) ? "Y" : "N");
00587 printf("LNE prescale : %s \n",(csr & IS_LNE) ? "Y" : "N");
00588 printf("Reference pulse 1: %s \t",(csr & IS_REF1) ? "Y" : "N");
00589 printf("Next Logic : %s \n",(csr & IS_NEXT_LOGIC_ENABLE) ? "Y" : "N");
00590 printf("FIFO empty : %s \t",(csr & IS_FIFO_EMPTY ) ? "Y" : "N");
00591 printf("FIFO almost empty: %s \t",(csr & IS_FIFO_ALMOST_EMPTY) ? "Y" : "N");
00592 printf("FIFO half full : %s \t",(csr & IS_FIFO_HALF_FULL) ? "Y" : "N");
00593 printf("FIFO full : %s \n",(csr & IS_FIFO_FULL) ? "Y" : "N");
00594 printf("External next : %s \t",(csr & IS_EXTERN_NEXT) ? "Y" : "N");
00595 printf("External clear : %s \t",(csr & IS_EXTERN_CLEAR) ? "Y" : "N");
00596 printf("External disable : %s \t",(csr & IS_EXTERN_DISABLE) ? "Y" : "N");
00597 printf("Software couting : %s \n",(csr & IS_SOFT_COUNTING) ? "N" : "Y");
00598 printf("IRQ enable CIP : %s \t",(csr & IS_IRQ_EN_CIP) ? "Y" : "N");
00599 printf("IRQ enable FULL : %s \t",(csr & IS_IRQ_EN_FULL) ? "Y" : "N");
00600 printf("IRQ enable HFULL : %s \t",(csr & IS_IRQ_EN_HFULL) ? "Y" : "N");
00601 printf("IRQ enable ALFULL: %s \n",(csr & IS_IRQ_EN_ALFULL) ? "Y" : "N");
00602 printf("IRQ CIP : %s \t",(csr & IS_IRQ_CIP) ? "Y" : "N");
00603 printf("IRQ FIFO full : %s \t",(csr & IS_IRQ_FULL) ? "Y" : "N");
00604 printf("IRQ FIFO 1/2 full: %s \t",(csr & IS_IRQ_HFULL) ? "Y" : "N");
00605 printf("IRQ FIFO almost F: %s \n",(csr & IS_IRQ_ALFULL) ? "Y" : "N");
00606 printf("internal VME IRQ : %s \t",(csr & 0x4000000) ? "Y" : "N");
00607 printf("VME IRQ : %s \n",(csr & 0x8000000) ? "Y" : "N");
00608 }
00609
00610 int intflag=0;
00611
00612 static void myisr(int sig, siginfo_t * siginfo, void *extra)
00613 {
00614
00615
00616
00617
00618 if (intflag == 0) {
00619 intflag = 1;
00620 printf("interrupt: level:%d Vector:0x%x ... "
00621 , int_info.level, siginfo->si_value.sival_int & 0xFF);
00622 }
00623 }
00624
00625
00626
00627
00628 #ifdef MAIN_ENABLE
00629
00630 #define IRQ_VECTOR_CIP 0x70
00631 #define IRQ_LEVEL 5
00632
00633 int main (int argc, char* argv[]) {
00634
00635 int status, i;
00636 DWORD SIS3801_BASE = 0x110000;
00637 DWORD *pfifo=NULL, nwords;
00638
00639 MVME_INTERFACE *myvme;
00640
00641 if (argc>1) {
00642 sscanf(argv[1],"%x",&SIS3801_BASE);
00643 }
00644
00645
00646 status = mvme_open(&myvme, 0);
00647
00648
00649 mvme_set_am(myvme, MVME_AM_A24_ND);
00650
00651
00652 mvme_set_dmode(myvme, MVME_DMODE_D32);
00653
00654
00655 #if 0 // simple
00656 printf("ID:%x\n", sis3801_module_ID(myvme, SIS3801_BASE));
00657 sis3801_Status(myvme, SIS3801_BASE);
00658
00659 for(i=0;i<4;i++) {
00660 sis3801_CSR_write(myvme, SIS3801_BASE, LED_ON);
00661 usleep(500000);
00662 sis3801_CSR_write(myvme, SIS3801_BASE, LED_OFF);
00663 usleep(500000);
00664 }
00665 #endif
00666
00667 #if 1 // full acq with interrupts
00668
00669 sis3801_module_reset(myvme, SIS3801_BASE);
00670
00671 sis3801_channel_enable(myvme, SIS3801_BASE, 4);
00672
00673 sis3801_ref1(myvme, SIS3801_BASE, SIS3801_ENABLE_REF_CH1_WO);
00674
00675 sis3801_input_mode(myvme, SIS3801_BASE, 0);
00676
00677 sis3801_dwell_time(myvme, SIS3801_BASE, 1000);
00678
00679 sis3801_CSR_write(myvme, SIS3801_BASE, DISABLE_EXTERN_NEXT);
00680 sis3801_CSR_write(myvme, SIS3801_BASE, DISABLE_EXTERN_DISABLE);
00681 sis3801_CSR_write(myvme, SIS3801_BASE, ENABLE_102LNE);
00682 sis3801_CSR_write(myvme, SIS3801_BASE, ENABLE_LNE);
00683 sis3801_CSR_write(myvme, SIS3801_BASE, DISABLE_TEST);
00684 sis3801_CSR_write(myvme, SIS3801_BASE, DISABLE_25MHZ);
00685
00686
00687 sis3801_int_attach(myvme, SIS3801_BASE, IRQ_VECTOR_CIP, IRQ_LEVEL, (void *)myisr);
00688
00689
00690 sis3801_int_source_enable(myvme, SIS3801_BASE, SOURCE_FIFO_HFULL);
00691
00692
00693 sis3801_next_logic(myvme, SIS3801_BASE, SIS3801_ENABLE_NEXT_CLK_WO);
00694
00695 printf("CSR:0x%x\n", sis3801_CSR_read(myvme, SIS3801_BASE, CSR_FULL));
00696 sis3801_Status(myvme, SIS3801_BASE);
00697
00698 pfifo = (DWORD *) malloc(100000);
00699
00700 for (;;) {
00701 nwords = sis3801_HFIFO_read(myvme, SIS3801_BASE, pfifo);
00702 if (nwords) {
00703 for (i=0;i<32;i++) {
00704 printf("%d:0x%x ",i, pfifo[i]);
00705 }
00706
00707
00708 intflag = 0;
00709 }
00710 printf("CSR:0x%x\n", sis3801_CSR_read(myvme, SIS3801_BASE, CSR_FULL));
00711 usleep(500000);
00712 }
00713
00714 #endif
00715
00716 status = mvme_close(myvme);
00717 return 1;
00718 }
00719 #endif
00720
00721
00722
00723
00724
00725
00726
00727
00728