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00010 #include <stdio.h>
00011 #include <string.h>
00012 #include <stdlib.h>
00013 #include <assert.h>
00014
00015 #include "vf48.h"
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028 static int idx = 0, inbuf;
00029 int vf48_EventRead64(MVME_INTERFACE *mvme, DWORD base, DWORD *pdest, int *nentry)
00030 {
00031 int markerfound, j;
00032 DWORD lData[VF48_IDXMAX];
00033 DWORD *phead;
00034
00035 int cmode, timeout;
00036
00037 mvme_get_dmode(mvme, &cmode);
00038 mvme_set_dmode(mvme, MVME_DMODE_D32);
00039
00040 if (inbuf > VF48_IDXMAX) idx = 0;
00041
00042 if (idx == 0) {
00043 inbuf = vf48_NFrameRead(mvme, base);
00044
00045 vf48_DataRead(mvme, base, lData, &inbuf);
00046
00047 }
00048
00049
00050 timeout = 16;
00051 markerfound = 0;
00052 while (timeout) {
00053
00054 while ((idx < inbuf) && ((lData[idx] & 0xF0000000) != VF48_HEADER)) {
00055 idx++;
00056 }
00057 if (idx < inbuf) {
00058
00059 timeout = 0;
00060 phead = pdest;
00061 markerfound = 1;
00062
00063 *pdest++ = lData[idx];
00064 lData[idx] = 0xffffffff;
00065 idx++;
00066 } else {
00067
00068 timeout--;
00069 inbuf = vf48_NFrameRead(mvme, base);
00070
00071 idx = 0;
00072 vf48_DataRead(mvme, base, lData, &inbuf);
00073
00074 }
00075 }
00076 if ((timeout == 0) && !markerfound) {
00077
00078 idx = 0;
00079 *nentry = 0;
00080 return VF48_ERROR;
00081 }
00082
00083
00084 timeout = 64;
00085 while(timeout) {
00086 timeout--;
00087
00088 while ((idx < inbuf) && ((lData[idx] & 0xF0000000) != VF48_TRAILER)) {
00089 *pdest++ = lData[idx++];
00090 }
00091 if ((lData[idx] & 0xF0000000) == VF48_TRAILER) {
00092
00093 *pdest++ = lData[idx++];
00094 *nentry = pdest - phead;
00095
00096 return SUCCESS;
00097 } else {
00098
00099
00100 j = 40000;
00101 while (j) { j--; }
00102
00103 inbuf = vf48_NFrameRead(mvme, base);
00104 vf48_DataRead(mvme, base, lData, &inbuf);
00105 idx = 0;
00106
00107 }
00108 if (timeout == 0) {
00109 printf("vf48_EventRead: Trailer Loop: Timeout Trailer not found\n");
00110 idx = 0;
00111 *nentry = 0;
00112 return VF48_ERROR;
00113 }
00114 }
00115 printf(" coming out from here\n");
00116 return VF48_ERROR;
00117 }
00118
00119
00120
00121
00122
00123
00124
00125
00126
00127
00128 int vf48_EventRead(MVME_INTERFACE *mvme, DWORD base, DWORD *pdest, int *nentry)
00129 {
00130 int cmode, timeout, nframe;
00131 DWORD hdata;
00132
00133 mvme_get_dmode(mvme, &cmode);
00134 mvme_set_dmode(mvme, MVME_DMODE_D32);
00135
00136 *nentry = 0;
00137 nframe = mvme_read_value(mvme, base+VF48_NFRAME_R);
00138
00139
00140 timeout=25000;
00141 if (nframe) {
00142 do {
00143 timeout--;
00144 hdata = mvme_read_value(mvme, base+VF48_DATA_FIFO_R);
00145 } while (!((hdata & 0xF0000000) == VF48_HEADER) && (timeout));
00146
00147 if (timeout == 0) {
00148 *nentry = 0;
00149
00150 mvme_set_dmode(mvme, cmode);
00151 return VF48_ERR_NODATA;
00152 }
00153
00154
00155 pdest[*nentry] = hdata;
00156 *nentry += 1;
00157 timeout=25000;
00158
00159 do {
00160 pdest[*nentry] = mvme_read_value(mvme, base+VF48_DATA_FIFO_R);
00161
00162 timeout--;
00163 *nentry += 1;
00164 } while (!((pdest[*nentry-1] & 0xF0000000) == VF48_TRAILER) && timeout);
00165 if (timeout == 0) {
00166 printf("timeout on Trailer data:0x%x\n", pdest[*nentry-1]);
00167 printf("nentry:%d data:0x%x base:0x%x \n", *nentry, pdest[*nentry], base+VF48_DATA_FIFO_R);
00168 *nentry = 0;
00169 return VF48_ERROR;
00170 }
00171 nentry--;
00172 }
00173 mvme_set_dmode(mvme, cmode);
00174 return (VF48_SUCCESS);
00175 }
00176
00177
00178
00179
00180
00181
00182
00183
00184
00185 int vf48_DataRead(MVME_INTERFACE *mvme, DWORD base, DWORD *pdest, int *nentry)
00186 {
00187 int status;
00188
00189 mvme_set_am( mvme, MVME_AM_A24);
00190 mvme_set_dmode( mvme, MVME_DMODE_D32);
00191 mvme_set_blt( mvme, MVME_BLT_MBLT64);
00192
00193
00194
00195
00196
00197 status = mvme_read(mvme, pdest, base+VF48_DATA_FIFO_R, *nentry<<2);
00198 if (status != MVME_SUCCESS)
00199 return 0;
00200
00201 return (*nentry);
00202 }
00203
00204
00205 int vf48_ParameterWrite(MVME_INTERFACE *mvme, DWORD base, int grp, int param, int value)
00206 {
00207 int retry;
00208 int cmode;
00209
00210 if (grp < 6) {
00211 switch (param) {
00212 case VF48_SEGMENT_SIZE:
00213 if (value > 1023) {
00214 value = 1023;
00215 printf("vf48_ParameterWrite: Segment size troncated to 1023\n");
00216 }
00217 break;
00218 case VF48_PRE_TRIGGER:
00219 if (value > 127) {
00220 value = 100;
00221 printf("vf48_ParameterWrite: Pre trigger troncated to 100\n");
00222 }
00223 break;
00224 case VF48_LATENCY:
00225 if (value > 127) {
00226 value = 127;
00227 printf("vf48_ParameterWrite: Latency troncated to 127\n");
00228 }
00229 break;
00230 };
00231 mvme_get_dmode(mvme, &cmode);
00232 mvme_set_dmode(mvme, MVME_DMODE_D32);
00233
00234 if (0) {
00235 int csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00236 printf("Writing grp %d, param %d, ID_RDY %d, DATA_RDY %d\n", grp, param, csr & VF48_CSR_PARM_ID_RDY, csr & VF48_CSR_PARM_DATA_RDY);
00237 }
00238
00239 for (retry=20; retry>0; retry--) {
00240 int to;
00241 int wr;
00242 int rd;
00243
00244
00245 for (to=10; to>0; to--) {
00246 int csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00247
00248 if (csr & VF48_CSR_PARM_ID_RDY)
00249 break;
00250 }
00251
00252 if (to<=0)
00253 printf("vf48_ParameterWrite: Group %d, parameter %d, timeout waiting for VF48_CSR_PARM_ID_RDY\n", grp, param);
00254
00255 wr = param | grp<<VF48_GRP_OFFSET;
00256 mvme_write_value(mvme, base+VF48_PARAM_ID_W, wr);
00257
00258
00259 mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00260
00261 mvme_write_value(mvme, base+VF48_PARAM_DATA_RW, value);
00262
00263
00264 mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00265
00266 rd = vf48_ParameterRead(mvme, base, grp, param);
00267
00268
00269
00270 if (rd == value) {
00271 mvme_set_dmode(mvme, cmode);
00272 return VF48_SUCCESS;
00273 }
00274
00275 printf("vf48_ParameterWrite: Module at 0x%x, Group %d, parameter %d: data mismatch error: wrote 0x%08x, read 0x%08x\n", base, grp, param, value, rd);
00276 }
00277
00278 fprintf(stderr, "vf48_ParameterWrite: Group %d, parameter %d, too many retries writing VF48 parameter!\n", grp, param);
00279 exit(1);
00280 }
00281 return VF48_ERR_PARM;
00282 }
00283
00284
00285
00286
00287
00288
00289
00290
00291
00292
00293 int vf48_ParameterRead(MVME_INTERFACE *mvme, DWORD base, int grp, int param)
00294 {
00295 int cmode, par, to, wr, retry;
00296 int debug = 0;
00297
00298 if (vf48_isPresent(mvme, base) != VF48_SUCCESS) {
00299 printf("There is no VF48 at VME A24 0x%x\n", base);
00300 return VF48_ERR_PARM;
00301 }
00302
00303 if (grp < 6) {
00304 mvme_get_dmode(mvme, &cmode);
00305 mvme_set_dmode(mvme, MVME_DMODE_D32);
00306
00307 for (retry=50; retry>0; retry--) {
00308
00309 int csr = 0;
00310
00311 if (debug) {
00312 csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00313 printf("Reading grp %d, param %d, ID_RDY %d, DATA_RDY %d\n", grp, param, csr & VF48_CSR_PARM_ID_RDY, csr & VF48_CSR_PARM_DATA_RDY);
00314 }
00315
00316
00317 for (to=10; to>0; to--) {
00318 csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00319 if (debug)
00320 printf("vf48_ParameterRead: read1: Waiting for 0x%x, CSR 0x%x, to %d\n", VF48_CSR_PARM_ID_RDY, csr, to);
00321 if (csr & VF48_CSR_PARM_ID_RDY)
00322 break;
00323 }
00324
00325 if (debug)
00326 printf("vf48_ParameterRead: Group %d, parameter %d, VF48_CSR_PARAM_ID_RDY wait %d\n", grp, param, to);
00327
00328
00329 if (to<=0) {
00330
00331
00332 }
00333
00334 wr = VF48_PARMA_BIT_RD | param | grp<<VF48_GRP_OFFSET;
00335
00336 mvme_write_value(mvme, base+VF48_PARAM_ID_W, wr);
00337
00338
00339 mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00340
00341
00342
00343 mvme_write_value(mvme, base+VF48_PARAM_DATA_RW, 0xFFFFFFFF);
00344
00345
00346
00347 mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00348
00349
00350 for (to=10; to>0; to--) {
00351 csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00352 if (debug)
00353 printf("vf48_ParameterRead: CSR 0x%x, Waiting for 0x%x, TO %d\n", csr, VF48_CSR_PARM_DATA_RDY, to);
00354 if (csr & VF48_CSR_PARM_DATA_RDY)
00355 break;
00356 }
00357
00358 if (csr & VF48_CSR_CRC_ERROR) {
00359 if (0)
00360 printf("vf48_ParameterRead: CSR 0x%x, CRC error!\n", csr);
00361
00362 }
00363
00364 if (csr & VF48_CSR_PARM_DATA_RDY) {
00365
00366 int data = mvme_read_value(mvme, base+VF48_PARAM_DATA_RW);
00367
00368 csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00369
00370 if (debug)
00371 printf("vf48_ParameterRead: CSR 0x%x, data 0x%x\n", csr, data);
00372
00373 if ((csr & VF48_CSR_PARM_DATA_RDY) == 0) {
00374 mvme_set_dmode(mvme, cmode);
00375 return data;
00376 }
00377 }
00378
00379 if (csr & VF48_CSR_PARM_DATA_RDY) {
00380 csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00381 printf("vf48_ParameterRead: CSR 0x%x, stuck VF48_CSR_PARM_DATA_RDY\n", csr);
00382 }
00383
00384 if (debug)
00385 printf("vf48_ParameterRead: Group %d, parameter %d, timeout waiting for VF48_CSR_PARAM_DATA_RDY, retry %d\n", grp, param, retry);
00386
00387 }
00388
00389 fprintf(stderr, "vf48_ParameterRead: Group %d, parameter %d, too many retries reading vf48 parameter!\n", grp, param);
00390 exit(1);
00391 }
00392 return VF48_ERR_PARM;
00393 }
00394
00395
00396 int vf48_Reset(MVME_INTERFACE *mvme, DWORD base)
00397 {
00398 int cmode, v;
00399
00400 mvme_get_dmode(mvme, &cmode);
00401 mvme_set_dmode(mvme, MVME_DMODE_D32);
00402 if (1)
00403 printf("vf48_Reset: CSR 0x%x\n", mvme_read_value(mvme, base+VF48_CSR_REG_RW));
00404 mvme_write_value(mvme, base+VF48_GLOBAL_RESET_W, 0);
00405
00406 if (1)
00407 printf("vf48_Reset: CSR 0x%x\n", mvme_read_value(mvme, base+VF48_CSR_REG_RW));
00408 mvme_write_value(mvme, base+VF48_TEST_REG_RW, 0x00000000);
00409 v = mvme_read_value(mvme, base+VF48_TEST_REG_RW);
00410 if (v != 0)
00411 printf("vf48_Reset: Test register data mismatch: read 0x%08x, expected 0\n", v);
00412 mvme_write_value(mvme, base+VF48_TEST_REG_RW, 0x0000FFFF);
00413 v = mvme_read_value(mvme, base+VF48_TEST_REG_RW);
00414 if (v != 0x0000FFFF)
00415 printf("vf48_Reset: Test register data mismatch: read 0x%08x, expected 0x0000FFFF\n", v);
00416 mvme_set_dmode(mvme, cmode);
00417
00418 if (vf48_isPresent(mvme, base) != VF48_SUCCESS) {
00419 printf("There is no VF48 at VME A24 0x%x\n", base);
00420 return VF48_ERR_HW;
00421 }
00422
00423 return VF48_SUCCESS;
00424 }
00425
00426
00427 int vf48_AcqStart(MVME_INTERFACE *mvme, DWORD base)
00428 {
00429 int cmode, csr;
00430
00431 mvme_get_dmode(mvme, &cmode);
00432 mvme_set_dmode(mvme, MVME_DMODE_D32);
00433 mvme_set_am(mvme, MVME_AM_A24);
00434 csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00435 csr |= VF48_CSR_START_ACQ;
00436 mvme_write_value(mvme, base+VF48_CSR_REG_RW, csr);
00437 mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00438 mvme_set_dmode(mvme, cmode);
00439 return VF48_SUCCESS;
00440
00441 #if 0
00442 status = mvme_read_value(mvme, base+VF48_NFRAME_R);
00443 if (status <= 0xFF) {
00444 mvme_write_value(mvme, base+VF48_SELECTIVE_SET_W, VF48_CSR_ACTIVE_ACQ);
00445 }
00446 mvme_set_dmode(mvme, cmode);
00447 return (status > 0xFF ? VF48_ERR_HW : VF48_SUCCESS);
00448 #endif
00449 }
00450
00451
00452 int vf48_AcqStop(MVME_INTERFACE *mvme, DWORD base)
00453 {
00454 int cmode, csr;
00455
00456 mvme_get_dmode(mvme, &cmode);
00457 mvme_set_am(mvme, MVME_AM_A24);
00458 mvme_set_dmode(mvme, MVME_DMODE_D32);
00459 csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00460 csr &= ~(VF48_CSR_START_ACQ);
00461 mvme_write_value(mvme, base+VF48_CSR_REG_RW, csr);
00462 mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00463 mvme_set_dmode(mvme, cmode);
00464 return VF48_SUCCESS;
00465
00466 #if 0
00467 status = mvme_read_value(mvme, base+VF48_NFRAME_R);
00468 if (status <= 0xFF) {
00469 mvme_write_value(mvme, base+VF48_SELECTIVE_CLR_W, VF48_CSR_ACTIVE_ACQ);
00470 }
00471 mvme_set_dmode(mvme, cmode);
00472 return (status > 0xFF ? VF48_ERR_HW : VF48_SUCCESS);
00473 #endif
00474 }
00475
00476
00477
00478
00479
00480
00481
00482
00483 int vf48_ExtTrgSet(MVME_INTERFACE *mvme, DWORD base)
00484 {
00485 int cmode, csr;
00486 mvme_get_dmode(mvme, &cmode);
00487 mvme_set_dmode(mvme, MVME_DMODE_D32);
00488 csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00489 csr |= VF48_CSR_EXT_TRIGGER;
00490 mvme_write_value(mvme, base+VF48_CSR_REG_RW, csr);
00491 mvme_set_dmode(mvme, cmode);
00492 return VF48_SUCCESS;
00493 }
00494
00495
00496
00497
00498
00499
00500
00501
00502 int vf48_ExtTrgClr(MVME_INTERFACE *mvme, DWORD base)
00503 {
00504 int cmode, csr;
00505
00506 mvme_get_dmode(mvme, &cmode);
00507 mvme_set_dmode(mvme, MVME_DMODE_D32);
00508 csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00509 csr &= ~(VF48_CSR_EXT_TRIGGER);
00510 mvme_write_value(mvme, base+VF48_CSR_REG_RW, csr);
00511 mvme_set_dmode(mvme, cmode);
00512 return VF48_SUCCESS;
00513 }
00514
00515
00516 int vf48_NFrameRead(MVME_INTERFACE *mvme, DWORD base)
00517 {
00518 int cmode, nframe;
00519
00520
00521 mvme_set_am(mvme, MVME_AM_A24);
00522 mvme_get_dmode(mvme, &cmode);
00523 mvme_set_dmode(mvme, MVME_DMODE_D32);
00524 nframe = mvme_read_value(mvme, base+VF48_NFRAME_R);
00525 mvme_set_dmode(mvme, cmode);
00526 return (nframe);
00527 }
00528
00529
00530 int vf48_CsrRead(MVME_INTERFACE *mvme, DWORD base)
00531 {
00532 int cmode, csr;
00533
00534 mvme_get_dmode(mvme, &cmode);
00535 mvme_set_dmode(mvme, MVME_DMODE_D16);
00536 csr = mvme_read_value(mvme, base+VF48_CSR_REG_RW);
00537 mvme_set_dmode(mvme, cmode);
00538 return csr;
00539 }
00540
00541
00542 int vf48_FeFull(MVME_INTERFACE *mvme, DWORD base)
00543 {
00544 int cmode, fefull;
00545
00546 mvme_get_dmode(mvme, &cmode);
00547 mvme_set_dmode(mvme, MVME_DMODE_D32);
00548 fefull = mvme_read_value(mvme, base+VF48_CSR_REG_RW) & VF48_CSR_FE_FULL;
00549 mvme_set_dmode(mvme, cmode);
00550 return fefull;
00551 }
00552
00553
00554 int vf48_FeNotEmpty(MVME_INTERFACE *mvme, DWORD base)
00555 {
00556 int cmode, fenotempty;
00557
00558 mvme_get_dmode(mvme, &cmode);
00559 mvme_set_dmode(mvme, MVME_DMODE_D32);
00560 fenotempty = mvme_read_value(mvme, base+VF48_CSR_REG_RW) & VF48_CSR_FE_NOTEMPTY;
00561 mvme_set_dmode(mvme, cmode);
00562 return fenotempty;
00563 }
00564
00565
00566 int vf48_GrpEnable(MVME_INTERFACE *mvme, DWORD base, int grpbit)
00567 {
00568 int cmode;
00569
00570 mvme_get_dmode(mvme, &cmode);
00571 mvme_set_dmode(mvme, MVME_DMODE_D16);
00572 grpbit &= 0x3F;
00573 mvme_write_value(mvme, base+VF48_GRP_REG_RW, grpbit);
00574 mvme_set_dmode(mvme, cmode);
00575 return VF48_SUCCESS;
00576 }
00577
00578
00579 int vf48_GrpRead(MVME_INTERFACE *mvme, DWORD base)
00580 {
00581 int cmode,grp;
00582
00583 mvme_get_dmode(mvme, &cmode);
00584 mvme_set_dmode(mvme, MVME_DMODE_D16);
00585 grp = mvme_read_value(mvme, base+VF48_GRP_REG_RW);
00586 mvme_set_dmode(mvme, cmode);
00587 return grp;
00588 }
00589
00590
00591
00592
00593
00594 int vf48_SegmentSizeSet(MVME_INTERFACE *mvme, DWORD base, DWORD size)
00595 {
00596 int cmode, i;
00597
00598 mvme_get_dmode(mvme, &cmode);
00599 mvme_set_dmode(mvme, MVME_DMODE_D16);
00600 for (i=0;i<6;i++)
00601 vf48_ParameterWrite(mvme, base, i, VF48_SEGMENT_SIZE, size);
00602 mvme_set_dmode(mvme, cmode);
00603 return 1;
00604 }
00605
00606
00607
00608
00609
00610
00611 int vf48_SegmentSizeRead(MVME_INTERFACE *mvme, DWORD base, int grp)
00612 {
00613 int cmode, val;
00614
00615 mvme_get_dmode(mvme, &cmode);
00616 mvme_set_dmode(mvme, MVME_DMODE_D16);
00617 val = vf48_ParameterRead(mvme, base, grp, VF48_SEGMENT_SIZE);
00618 mvme_set_dmode(mvme, cmode);
00619 return val;
00620 }
00621
00622
00623
00624
00625
00626
00627
00628
00629 int vf48_TrgThresholdSet(MVME_INTERFACE *mvme, DWORD base, int grp, DWORD size)
00630 {
00631 int cmode;
00632
00633 mvme_get_dmode(mvme, &cmode);
00634 mvme_set_dmode(mvme, MVME_DMODE_D16);
00635 vf48_ParameterWrite(mvme, base, grp, VF48_TRIG_THRESHOLD, size);
00636 mvme_set_dmode(mvme, cmode);
00637 return grp;
00638 }
00639
00640
00641
00642
00643
00644 int vf48_TrgThresholdRead(MVME_INTERFACE *mvme, DWORD base, int grp)
00645 {
00646 int cmode, val;
00647
00648 mvme_get_dmode(mvme, &cmode);
00649 mvme_set_dmode(mvme, MVME_DMODE_D16);
00650 val = vf48_ParameterRead(mvme, base, grp, VF48_TRIG_THRESHOLD);
00651 mvme_set_dmode(mvme, cmode);
00652 return val;
00653 }
00654
00655
00656
00657
00658
00659
00660
00661
00662
00663
00664 int vf48_HitThresholdSet(MVME_INTERFACE *mvme, DWORD base, int grp, DWORD size)
00665 {
00666 int cmode;
00667
00668 mvme_get_dmode(mvme, &cmode);
00669 mvme_set_dmode(mvme, MVME_DMODE_D16);
00670 vf48_ParameterWrite(mvme, base, grp, VF48_HIT_THRESHOLD, size);
00671 mvme_set_dmode(mvme, cmode);
00672 return grp;
00673 }
00674
00675
00676
00677
00678
00679 int vf48_HitThresholdRead(MVME_INTERFACE *mvme, DWORD base, int grp)
00680 {
00681 int cmode, val;
00682
00683 mvme_get_dmode(mvme, &cmode);
00684 mvme_set_dmode(mvme, MVME_DMODE_D16);
00685 val = vf48_ParameterRead(mvme, base, grp, VF48_HIT_THRESHOLD);
00686 mvme_set_dmode(mvme, cmode);
00687 return val;
00688 }
00689
00690
00691
00692
00693
00694
00695 int vf48_ActiveChMaskSet(MVME_INTERFACE *mvme, DWORD base, int grp, DWORD size)
00696 {
00697 int cmode;
00698
00699 mvme_get_dmode(mvme, &cmode);
00700 mvme_set_dmode(mvme, MVME_DMODE_D16);
00701 vf48_ParameterWrite(mvme, base, grp, VF48_ACTIVE_CH_MASK, size);
00702 mvme_set_dmode(mvme, cmode);
00703 return grp;
00704 }
00705
00706
00707
00708
00709
00710 int vf48_ActiveChMaskRead(MVME_INTERFACE *mvme, DWORD base, int grp)
00711 {
00712 int cmode, val;
00713
00714 mvme_get_dmode(mvme, &cmode);
00715 mvme_set_dmode(mvme, MVME_DMODE_D16);
00716 val = vf48_ParameterRead(mvme, base, grp, VF48_ACTIVE_CH_MASK);
00717 mvme_set_dmode(mvme, cmode);
00718 return val;
00719 }
00720
00721
00722
00723
00724
00725
00726 int vf48_RawDataSuppSet(MVME_INTERFACE *mvme, DWORD base, int grp, DWORD size)
00727 {
00728 int cmode;
00729
00730 mvme_get_dmode(mvme, &cmode);
00731 mvme_set_dmode(mvme, MVME_DMODE_D16);
00732 vf48_ParameterWrite(mvme, base, grp, VF48_MBIT1, size);
00733 mvme_set_dmode(mvme, cmode);
00734 return grp;
00735 }
00736
00737
00738
00739
00740
00741 int vf48_RawDataSuppRead(MVME_INTERFACE *mvme, DWORD base, int grp)
00742 {
00743 int cmode, val;
00744
00745 mvme_get_dmode(mvme, &cmode);
00746 mvme_set_dmode(mvme, MVME_DMODE_D16);
00747 val = vf48_ParameterRead(mvme, base, grp, VF48_MBIT1);
00748 mvme_set_dmode(mvme, cmode);
00749 return val;
00750 }
00751
00752
00753
00754
00755
00756
00757
00758
00759
00760 int vf48_ChSuppSet(MVME_INTERFACE *mvme, DWORD base, int grp, DWORD value)
00761 {
00762 int cmode;
00763 int mbit2;
00764
00765 mvme_get_dmode(mvme, &cmode);
00766 mvme_set_dmode(mvme, MVME_DMODE_D16);
00767 mbit2 = vf48_ParameterRead(mvme, base, grp, VF48_MBIT2);
00768 mbit2 &= ~1;
00769 mbit2 |= value&0x1;
00770 vf48_ParameterWrite(mvme, base, grp, VF48_MBIT2, mbit2);
00771 mvme_set_dmode(mvme, cmode);
00772 return grp;
00773 }
00774
00775
00776
00777
00778
00779 int vf48_ChSuppRead(MVME_INTERFACE *mvme, DWORD base, int grp)
00780 {
00781 int cmode, val;
00782
00783 mvme_get_dmode(mvme, &cmode);
00784 mvme_set_dmode(mvme, MVME_DMODE_D16);
00785 val = 0x1 & vf48_ParameterRead(mvme, base, grp, VF48_MBIT2);
00786 mvme_set_dmode(mvme, cmode);
00787 return val;
00788 }
00789
00790
00791
00792
00793
00794
00795
00796 int vf48_DivisorWrite(MVME_INTERFACE *mvme, DWORD base, DWORD value)
00797 {
00798 int cmode, i, mbit2;
00799
00800 assert(value > 0);
00801 assert(value < 256);
00802
00803 mvme_get_dmode(mvme, &cmode);
00804 mvme_set_dmode(mvme, MVME_DMODE_D16);
00805 for (i=0;i<6;i++) {
00806 mbit2 = vf48_ParameterRead(mvme, base, i, VF48_MBIT2);
00807 mbit2 &= ~0xFF00;
00808 mbit2 |= (value << 8);
00809 vf48_ParameterWrite(mvme, base, i, VF48_MBIT2, mbit2);
00810 }
00811 for (i=0;i<6;i++) {
00812 int rd = vf48_DivisorRead(mvme, base, i);
00813 if (rd != value) {
00814 printf("vf48_DivisorWrite: Divisor read back mismatch: module at 0x%x, group %d, wrote %d, read back %d\n", base, i, value, rd);
00815 abort();
00816 }
00817 }
00818 mvme_set_dmode(mvme, cmode);
00819 return value;
00820 }
00821
00822
00823
00824
00825
00826
00827 int vf48_DivisorRead(MVME_INTERFACE *mvme, DWORD base, int grp)
00828 {
00829 int cmode, val;
00830
00831 mvme_get_dmode(mvme, &cmode);
00832 mvme_set_dmode(mvme, MVME_DMODE_D16);
00833 val = vf48_ParameterRead(mvme, base, grp, VF48_MBIT2);
00834 val = (val >> 8) & 0xff;
00835 mvme_set_dmode(mvme, cmode);
00836 return val;
00837 }
00838
00839
00840 int vf48_Trigger(MVME_INTERFACE *mvme, DWORD base)
00841 {
00842 int r;
00843
00844 mvme_write_value(mvme, base + VF48_SOFT_TRIG_W, 0);
00845 r = mvme_read_value(mvme, base + VF48_CSR_REG_RW);
00846
00847 return VF48_SUCCESS;
00848 }
00849
00850
00851 int vf48_Setup(MVME_INTERFACE *mvme, DWORD base, int mode)
00852 {
00853 int cmode, i;
00854
00855 mvme_get_dmode(mvme, &cmode);
00856 mvme_set_dmode(mvme, MVME_DMODE_D16);
00857
00858 switch (mode) {
00859 case 0x1:
00860 printf("Default setting after power up (mode:%d)\n", mode);
00861 printf("\n");
00862 break;
00863 case 0x2:
00864 printf("External Trigger (mode:%d)\n", mode);
00865 vf48_ExtTrgSet(mvme, base);
00866 break;
00867 case 0x3:
00868 printf("External Trigger, Seg Size=16 (mode:%d)\n", mode);
00869 vf48_ExtTrgSet(mvme, base);
00870 for (i=0;i<6;i++)
00871 vf48_ParameterWrite(mvme, base, i, VF48_SEGMENT_SIZE, 16);
00872 for (i=0;i<6;i++)
00873 printf("SegSize grp %i:%d\n", i, vf48_ParameterRead(mvme, base, i, VF48_SEGMENT_SIZE));
00874 break;
00875 default:
00876 printf("Unknown setup mode\n");
00877 mvme_set_dmode(mvme, cmode);
00878 return -1;
00879 }
00880 mvme_set_dmode(mvme, cmode);
00881 return 0;
00882
00883 }
00884
00885
00886
00887
00888
00889
00890
00891 int vf48_Status(MVME_INTERFACE *mvme, DWORD base)
00892 {
00893 char *parname[] = {
00894 "",
00895 "PED",
00896 "Hit Det Threshold",
00897 "Clip Delay",
00898 "PreTrigger",
00899 "Segment Size",
00900 "K",
00901 "L",
00902 "M",
00903 "Channel enable",
00904 "Mbits1",
00905 "Mbits2",
00906 "Latency",
00907 "Firmware ID",
00908 "Attenuator",
00909 "Trigger Threshold"
00910 };
00911
00912 int cmode, i, j;
00913
00914 mvme_get_dmode(mvme, &cmode);
00915 mvme_set_dmode(mvme, MVME_DMODE_D32);
00916
00917 printf("VF48 at VME A24 0x%06x, status:\n", base);
00918 printf(" CSR: 0x%08x\n", mvme_read_value(mvme, base + 0x0));
00919 printf(" Test reg: 0x%08x\n", mvme_read_value(mvme, base + 0x20));
00920 printf(" Firmware: 0x%08x\n", mvme_read_value(mvme, base + 0x30));
00921 printf(" Group enable: 0x%08x\n", mvme_read_value(mvme, base + 0x90));
00922 printf(" NbrFrames: 0x%08x\n", mvme_read_value(mvme, base + 0xA0));
00923
00924 if (mvme_read_value(mvme, base + 0x0) & 1) {
00925 printf("Module is in running mode: cannot read parameters\n");
00926 } else {
00927 printf("Parameters:\n");
00928 for (i=1; i<16; i++) {
00929 printf(" par%02d (%-20s): ", i, parname[i]);
00930 for (j=0; j<6; j++) {
00931 int v = vf48_ParameterRead(mvme, base, j, i);
00932 printf(" %6d (0x%04x) ", v, v);
00933 }
00934 printf("\n");
00935 }
00936 }
00937
00938 mvme_set_dmode(mvme, cmode);
00939 return VF48_SUCCESS;
00940 }
00941
00942
00943
00944
00945
00946
00947
00948 int vf48_isPresent(MVME_INTERFACE *mvme, DWORD base)
00949 {
00950 int cmode;
00951 int missing = 0;
00952
00953 mvme_get_dmode(mvme, &cmode);
00954 mvme_set_dmode(mvme, MVME_DMODE_D32);
00955
00956 missing |= (0xFFFFFFFF==mvme_read_value(mvme, base + 0x0));
00957 missing |= (0xFFFFFFFF==mvme_read_value(mvme, base + 0x30));
00958
00959 mvme_set_dmode(mvme, cmode);
00960
00961 if (missing)
00962 return VF48_ERROR;
00963
00964 return VF48_SUCCESS;
00965 }
00966
00967
00968 #ifdef MAIN_ENABLE
00969 int main (int argc, char* argv[]) {
00970
00971 MVME_INTERFACE *myvme;
00972
00973 DWORD VF48_BASE = 0xAF0000;
00974 DWORD buf[200000], buf1[200000], buf2[200000];
00975 DWORD evt=0;
00976 int status, i, nframe, nframe1, nframe2, nentry, pnentry;
00977 int segsize = 10, latency=5, grpmsk = 0x3F, pretrig=0x20;
00978 int tthreshold = 10,hthreshold = 10, evtflag=0;
00979
00980
00981 status = mvme_open(&myvme, 0);
00982
00983
00984 mvme_set_am(myvme, MVME_AM_A24_ND);
00985
00986
00987 mvme_set_dmode(myvme, MVME_DMODE_D16);
00988
00989 #if 1
00990
00991 if (argc > 1) {
00992
00993 for (i=1;i<argc; i+=2) {
00994 if (argv[i][1] == 's') {
00995 segsize = atoi(argv[i+1]);
00996 }
00997 else if (argv[i][1] == 'l') {
00998 latency = atoi(argv[i+1]);
00999 }
01000 else if (argv[i][1] == 'p') {
01001 pretrig = atoi(argv[i+1]);
01002 }
01003 else if (argv[i][1] == 't') {
01004 tthreshold = atoi(argv[i+1]);
01005 }
01006 else if (argv[i][1] == 'u') {
01007 hthreshold = atoi(argv[i+1]);
01008 }
01009 else if (argv[i][1] == 'r') {
01010 i--;
01011 vf48_Reset(myvme, VF48_BASE);
01012 }
01013 else if (argv[i][1] == 'e') {
01014 evtflag = atoi(argv[i+1]);
01015 }
01016 else if (argv[i][1] == 'g') {
01017 grpmsk = strtol(argv[i+1], (char **)NULL, 16);
01018 }
01019 else if (argv[i][1] == 'h') {
01020 printf("\nvf48 : Run read only (no setup)\n");
01021 printf("vf48 -h : This help\n");
01022 printf("vf48 -r : Reset now\n");
01023 printf("vf48 -e val : Event flag for event display, 0, x, 64\n");
01024 printf("vf48 -s val : Setup Segment size value & Run [def:10]\n");
01025 printf("vf48 -l val : Setup Latency value & Run [def:5]\n");
01026 printf("vf48 -g 0xval: Setup Group Enable pattern & Run [def:0x3F]\n");
01027 printf("vf48 -p val : Setup PreTrigger & Run [def:0x20]\n");
01028 printf("vf48 -t val : Setup Trig Threshold & Run [def:0x0A]\n");
01029 printf("vf48 -u val : Setup Hit Threshold & Run [def:0x0A]\n");
01030 printf("Comments : Setup requires Run stopped\n\n");
01031 return 0;
01032 }
01033 }
01034
01035
01036 vf48_AcqStop(myvme, VF48_BASE);
01037
01038
01039 printf("Set Segment size to all grp to %d\n", segsize);
01040 for (i=0;i<6;i++) {
01041 vf48_ParameterWrite(myvme, VF48_BASE, i, VF48_SEGMENT_SIZE, segsize);
01042 printf("SegSize grp %i:%d\n", i, vf48_ParameterRead(myvme, VF48_BASE, i, VF48_SEGMENT_SIZE));
01043 }
01044
01045
01046 printf("Set Latency to all grp to %d\n", latency);
01047 for (i=0;i<6;i++) {
01048 vf48_ParameterWrite(myvme, VF48_BASE, i, VF48_LATENCY, latency);
01049 printf("Latency grp %i:%d\n", i, vf48_ParameterRead(myvme, VF48_BASE, i, VF48_LATENCY));
01050 }
01051
01052
01053 printf("Set PreTrigger to all grp to %d\n", pretrig);
01054 for (i=0;i<6;i++) {
01055 vf48_ParameterWrite(myvme, VF48_BASE, i, VF48_PRE_TRIGGER, pretrig);
01056 printf("Pre Trigger grp %i:%d\n", i, vf48_ParameterRead(myvme, VF48_BASE, i, VF48_PRE_TRIGGER));
01057 }
01058
01059
01060 printf("Set Trigger Threshold to all grp to %d\n", tthreshold);
01061 for (i=0;i<6;i++) {
01062 vf48_ParameterWrite(myvme, VF48_BASE, i, VF48_TRIG_THRESHOLD, tthreshold);
01063 printf("Trigger Threshold grp %i:%d\n", i, vf48_ParameterRead(myvme, VF48_BASE, i, VF48_TRIG_THRESHOLD));
01064 }
01065
01066
01067 printf("Set Hit Threshold to all grp to %d\n", hthreshold);
01068 for (i=0;i<6;i++) {
01069 vf48_ParameterWrite(myvme, VF48_BASE, i, VF48_HIT_THRESHOLD, hthreshold);
01070 printf("Hit Threshold grp %i:%d\n", i, vf48_ParameterRead(myvme, VF48_BASE, i, VF48_HIT_THRESHOLD));
01071 }
01072
01073
01074 for (i=0;i<6;i++)
01075 vf48_ParameterWrite(myvme, VF48_BASE, i, VF48_ACTIVE_CH_MASK, VF48_ALL_CHANNELS_ACTIVE);
01076
01077
01078 for (i=0;i<6;i++)
01079 vf48_ParameterWrite(myvme, VF48_BASE, i, VF48_MBIT1, VF48_RAW_DISABLE);
01080
01081
01082 for (i=0;i<6;i++)
01083 vf48_ParameterWrite(myvme, VF48_BASE, i, VF48_MBIT1, VF48_INVERSE_SIGNAL);
01084
01085
01086 for (i=0;i<6;i++)
01087 vf48_ParameterWrite(myvme, VF48_BASE, i, VF48_MBIT2, VF48_CH_SUPPRESS_ENABLE);
01088
01089
01090 printf("External Trigger\n");
01091 vf48_ExtTrgSet(myvme, VF48_BASE);
01092
01093
01094 vf48_GrpEnable(myvme, VF48_BASE, grpmsk);
01095 printf("Group Enable :0x%x\n", vf48_GrpRead(myvme, VF48_BASE));
01096
01097
01098 vf48_AcqStart(myvme, VF48_BASE);
01099
01100 printf("Run Started : CSR Buffer: 0x%x\n", vf48_CsrRead(myvme, VF48_BASE));
01101
01102 printf("Access mode:%d\n", evtflag);
01103
01104
01105 do {
01106
01107 nentry = vf48_NFrameRead(myvme, VF48_BASE);
01108 } while (nentry <= 0);
01109 printf("1 NFrame: 0x%x\n", nentry);
01110 }
01111
01112 #endif // if 0/1
01113
01114 if (evtflag == 0) {
01115 printf(" DataRead transfer\n");
01116 while (1)
01117 {
01118 usleep(100000);
01119 nframe = vf48_NFrameRead(myvme, VF48_BASE);
01120 if (nframe) {
01121
01122 nframe = vf48_NFrameRead(myvme, VF48_BASE);
01123 vf48_DataRead(myvme, VF48_BASE, (DWORD *)&buf, &nframe);
01124
01125 usleep(1000);
01126
01127 nframe1 = vf48_NFrameRead(myvme, VF48_BASE);
01128 vf48_DataRead(myvme, VF48_BASE, (DWORD *)&buf1, &nframe1);
01129 usleep(1000);
01130
01131 nframe2 = vf48_NFrameRead(myvme, VF48_BASE);
01132 vf48_DataRead(myvme, VF48_BASE, (DWORD *)&buf2, &nframe2);
01133
01134
01135
01136
01137
01138
01139
01140
01141
01142
01143
01144
01145
01146
01147 printf("End of Data for %d %d %d\n", nframe, nframe1, nframe2);
01148 }
01149 }
01150 }
01151
01152 if (evtflag == 64) {
01153 printf(" 64 bit transfer\n");
01154 while (1) {
01155 usleep(100000);
01156 nentry = 0;
01157 vf48_EventRead64(myvme, VF48_BASE, (DWORD *)&buf, &nentry);
01158 if (nentry != 0) {
01159 if (evt+1 != (buf[0] & 0xFFFFFF))
01160 printf(">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>--------------- Event# mismatch %x %x\n", evt, (buf[0] & 0xFFFFFF));
01161
01162 evt = (buf[0] & 0xFFFFFF);
01163
01164 for (i=0;i<nentry;i++) {
01165
01166 if ((buf[i] & 0xe0000000) == 0xe0000000 ||
01167 (buf[i] & 0x10000BAD) == 0x10000BAD)
01168 printf("\t\t\t\t\t\t\t\t %d buf[%d]:0x%x\n", nentry, i, buf[i]);
01169 }
01170
01171 if (pnentry != nentry)
01172 printf("End of Event previous(%d) (%d)\n", pnentry, nentry);
01173 else
01174 printf("End of Event (%d) T(0x%x)\n", nentry, buf[nentry]);
01175 pnentry = nentry;
01176 }
01177 }
01178 }
01179 else {
01180 printf(" 32 bit transfer\n");
01181 while (1) {
01182 usleep(100000);
01183 nentry = 0;
01184 vf48_EventRead(myvme, VF48_BASE, (DWORD *)&buf, &nentry);
01185 if (nentry != 0) {
01186 if (evt+1 != (buf[0] & 0xFFFFFF))
01187 printf("--------------- Event# mismatch %x %x\n", evt, (buf[0] & 0xFFFFFF));
01188
01189 evt = (buf[0] & 0xFFFFFF);
01190
01191 for (i=0;i<nentry;i++) {
01192 if ((buf[i] & 0xe0000000) == 0xe0000000)
01193 printf("\t\t\t\t\t\t\t\t %d buf[%d]:0x%x\n", nentry, i, buf[i]);
01194 }
01195
01196 if (pnentry != nentry)
01197 printf("End of Event previous(%d) (%d)\n", pnentry, nentry);
01198 else
01199 printf("End of Event (%d) T(0x%x)\n", nentry, buf[nentry]);
01200 pnentry = nentry;
01201 }
01202 }
01203 }
01204
01205
01206 status = mvme_close(myvme);
01207 return 1;
01208 }
01209 #endif