vmeio.c

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00001 /*********************************************************************
00002 
00003   Name:         vmeio.c
00004   Created by:   Pierre-Andre Amaudruz
00005 
00006   Cotents:      Routines for accessing the VMEIO Triumf board
00007 
00008   $Id: vmeio.c 4195 2008-05-14 05:03:56Z amaudruz $
00009 *********************************************************************/
00010 #include <stdio.h>
00011 #include <string.h>
00012 #include <unistd.h>
00013 #include <signal.h>
00014 #include "vmeio.h"
00015 
00016 /********************************************************************/
00017 /**
00018 Set output in pulse mode
00019 @param myvme vme structure
00020 @param base  VMEIO base address
00021 @param data  data to be written
00022 @return void
00023 */
00024 void vmeio_OutputSet(MVME_INTERFACE *myvme, DWORD base, DWORD data)
00025 {
00026   mvme_set_am(myvme, MVME_AM_A24_ND);
00027   mvme_set_dmode(myvme, MVME_DMODE_D32);
00028   mvme_write_value(myvme, base+VMEIO_OUTSET, data & 0xFFFFFF);
00029 }
00030 
00031 /********************************************************************/
00032 /**
00033 Write to the sync output (pulse mode)
00034 @param myvme vme structure
00035 @param base  VMEIO base address
00036 @param data  data to be written
00037 @return void
00038 */
00039 void vmeio_SyncWrite(MVME_INTERFACE *myvme, DWORD base, DWORD data)
00040 {
00041   mvme_set_am(myvme, MVME_AM_A24_ND);
00042   mvme_set_dmode(myvme, MVME_DMODE_D32);
00043   mvme_write_value(myvme, base+VMEIO_OUTPULSE, data & 0xFFFFFF);
00044 }
00045 
00046 /********************************************************************/
00047 /**
00048 Writee to the Async output (latch mode)
00049 @param myvme vme structure
00050 @param base  VMEIO base address
00051 @param data  data to be written
00052 @return void
00053 */
00054 void vmeio_AsyncWrite(MVME_INTERFACE *myvme, DWORD base, DWORD data)
00055 {
00056   mvme_set_am(myvme, MVME_AM_A24_ND);
00057   mvme_set_dmode(myvme, MVME_DMODE_D32);
00058   mvme_write_value(myvme, base+VMEIO_OUTLATCH, data & 0xFFFFFF);
00059 }
00060 
00061 /********************************************************************/
00062 /**
00063 Read the CSR register
00064 @param myvme vme structure
00065 @param base  VMEIO base address
00066 @return CSR status
00067 */
00068 int vmeio_CsrRead(MVME_INTERFACE *myvme, DWORD base)
00069 {
00070   int csr;
00071   mvme_set_am(myvme, MVME_AM_A24_ND);
00072   mvme_set_dmode(myvme, MVME_DMODE_D32);
00073   csr = mvme_read_value(myvme, base+VMEIO_RDCNTL);
00074   return (csr & 0xFF);
00075 }
00076 
00077 /********************************************************************/
00078 /**
00079 Read from the Async register
00080 @param myvme vme structure
00081 @param base  VMEIO base address
00082 @return Async_Reg
00083 */
00084 int vmeio_AsyncRead(MVME_INTERFACE *myvme, DWORD base)
00085 {
00086   int csr;
00087   mvme_set_am(myvme, MVME_AM_A24_ND);
00088   mvme_set_dmode(myvme, MVME_DMODE_D32);
00089   csr = mvme_read_value(myvme, base+VMEIO_RDASYNC);
00090   return (csr & 0xFFFFFF);
00091 }
00092 
00093 /********************************************************************/
00094 /**
00095 Read from the Sync register
00096 @param myvme vme structure
00097 @param base  VMEIO base address
00098 @return Sync_Reg
00099 */
00100 int vmeio_SyncRead(MVME_INTERFACE *myvme, DWORD base)
00101 {
00102   int csr;
00103   mvme_set_am(myvme, MVME_AM_A24_ND);
00104   mvme_set_dmode(myvme, MVME_DMODE_D32);
00105   csr = mvme_read_value(myvme, base+VMEIO_RDSYNC);
00106   return (csr & 0xFFFFFF);
00107 }
00108 
00109 /********************************************************************/
00110 /**
00111 Clear Strobe input
00112 @param myvme vme structure
00113 @param base  VMEIO base address
00114 @return void
00115 */
00116 void vmeio_StrobeClear(MVME_INTERFACE *myvme, DWORD base)
00117 {
00118   mvme_set_am(myvme, MVME_AM_A24_ND);
00119   mvme_set_dmode(myvme, MVME_DMODE_D32);
00120   mvme_write_value(myvme, base+VMEIO_RDCNTL, 0);
00121 }
00122 
00123 /********************************************************************/
00124 /**
00125 Enable Interrupt source.
00126 Only any of the first 8 inputs can generate interrupt.
00127 @param myvme vme structure
00128 @param base  VMEIO base address
00129 @param input inputs 0..7 (LSB)
00130 @return void
00131 */
00132 void vmeio_IntEnable(MVME_INTERFACE *myvme, DWORD base, int input)
00133 {
00134   mvme_set_am(myvme, MVME_AM_A24_ND);
00135   mvme_set_dmode(myvme, MVME_DMODE_D32);
00136   mvme_write_value(myvme, base+VMEIO_IRQENBL, input);
00137 }
00138 
00139 /********************************************************************/
00140 /**
00141 Select Interrupt source and arm interrupt
00142 The CSR should be reset before this operation.
00143 In Sync mode the strobe and the input have to be in coincidence.
00144 In Async mode a logical level on the input will trigger the interrupt.
00145 @param myvme vme structure
00146 @param base  VMEIO base address
00147 @param input inputs 0..7 if 1=> Sync, 0=> Async
00148 @return void
00149 */
00150 void vmeio_IntRearm(MVME_INTERFACE *myvme, DWORD base, int input)
00151 {
00152   mvme_set_am(myvme, MVME_AM_A24_ND);
00153   mvme_set_dmode(myvme, MVME_DMODE_D32);
00154   mvme_write_value(myvme, base+VMEIO_INTSRC, input);
00155 }
00156 
00157 
00158 /********************************************************************/
00159 /********************************************************************/
00160 static void myisrvmeio(int sig, siginfo_t * siginfo, void *extra)
00161 {
00162   fprintf(stderr, "myisrvmeio interrupt received \n");
00163 }
00164 
00165 
00166 #ifdef MAIN_ENABLE
00167 int main () {
00168 
00169   MVME_INTERFACE *myvme;
00170   int myinfo = 1; // VME_INTERRUPT_SIGEVENT;
00171 
00172   DWORD VMEIO_BASE = 0x780000;
00173   int status, csr;
00174   int      data=0xf;
00175 
00176   // Test under vmic
00177   status = mvme_open(&myvme, 0);
00178 
00179   // Set am to A24 non-privileged Data
00180   mvme_set_am(myvme, MVME_AM_A24_ND);
00181 
00182   // Set dmode to D32
00183   mvme_set_dmode(myvme, MVME_DMODE_D32);
00184 
00185   csr = vmeio_CsrRead(myvme, VMEIO_BASE);
00186   printf("CSR Buffer: 0x%x\n", csr);
00187 
00188   if (0) {
00189     // Set 0xF in pulse mode
00190     vmeio_OutputSet(myvme, VMEIO_BASE, 0xF);
00191 
00192     // Write latch mode
00193     vmeio_AsyncWrite(myvme, VMEIO_BASE, 0xc);
00194     vmeio_AsyncWrite(myvme, VMEIO_BASE, 0x0);
00195 
00196     // Read from the Async Reg
00197     data = vmeio_AsyncRead(myvme, VMEIO_BASE);
00198     printf("Async Buffer: 0x%x\n", data);
00199 
00200     // Read from the Sync Reg
00201     data = vmeio_SyncRead(myvme, VMEIO_BASE);
00202     printf("Sync Buffer: 0x%x\n", data);
00203 
00204     for (;;) {
00205       // Write pulse
00206       vmeio_SyncWrite(myvme, VMEIO_BASE, 0xF);
00207       vmeio_SyncWrite(myvme, VMEIO_BASE, 0xF);
00208     }
00209   }
00210 
00211   // Interrupt test
00212   if (0) {
00213     mvme_interrupt_attach(myvme, 7, 0x80, myisrvmeio, &myinfo);
00214 
00215     // Pulse on out 2 only
00216     vmeio_OutputSet(myvme, VMEIO_BASE, 0x2);
00217 
00218     // Enable Interrupts
00219     vmeio_IntEnable(myvme, VMEIO_BASE, 0x3);
00220 
00221     // Clear CSR
00222     vmeio_StrobeClear(myvme, VMEIO_BASE);
00223 
00224     // Select type and Rearm
00225     vmeio_IntRearm(myvme, VMEIO_BASE, 3);
00226 
00227     // Delay int generation
00228     //    udelay(1000000);
00229 
00230     // Write latch mode
00231     vmeio_AsyncWrite(myvme, VMEIO_BASE, 0xc);
00232     vmeio_AsyncWrite(myvme, VMEIO_BASE, 0x0);
00233 
00234     mvme_interrupt_detach(myvme, 1, 0x00, &myinfo);
00235   }
00236 
00237   // Interrupt test
00238   if (1) {
00239     /*
00240       start the code for listening to the IRQ7 vector:0x80
00241       use the script sample below to issue the interrupt.
00242       # set output latch mode
00243       vme_poke -a VME_A24UD -d VME_D32 -A 0x780008 0x0
00244       # write 1 latch on output 1  --> interrupt generated
00245       vme_poke -a VME_A24UD -d VME_D32 -A 0x780010 0x1
00246       # Enable interrupt 1
00247       vme_poke -a VME_A24UD -d VME_D32 -A 0x780000 0x1
00248       # Clear CSR
00249       vme_poke -a VME_A24UD -d VME_D32 -A 0x78001c 0x0
00250       # Rearm interrupt source for Async
00251       vme_poke -a VME_A24UD -d VME_D32 -A 0x780004 0x0
00252       # write 0 latch on output 1
00253       vme_poke -a VME_A24UD -d VME_D32 -A 0x780010 0x0
00254       # display CSR
00255       vme_peek -a VME_A24UD -d VME_D32 -A 0x78001c
00256      */
00257 
00258     mvme_interrupt_attach(myvme, 7, 0x80, myisrvmeio, &myinfo);
00259 
00260     for (;;) {
00261       printf(".");
00262       sleep(1);
00263       fflush(stdout);
00264     }
00265 
00266     mvme_interrupt_detach(myvme, 1, 0x00, &myinfo);
00267   }
00268   status = mvme_close(myvme);
00269   return 1;
00270 }
00271 #endif

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Contributions: Pierre-Andre Amaudruz - Sergio Ballestrero - Suzannah Daviel - Doxygen - Peter Green - Qing Gu - Greg Hackman - Gertjan Hofman - Paul Knowles - Exaos Lee - Rudi Meier - Glenn Moloney - Dave Morris - John M O'Donnell - Konstantin Olchanski - Renee Poutissou - Tamsen Schurman - Andreas Suter - Jan M.Wouters - Piotr Adam Zolnierczuk