PK __OBJSTORE__/PK __OBJSTORE__/Autonym/PK __OBJSTORE__/HierarchicalDesign/PK *__OBJSTORE__/HierarchicalDesign/HDProject/PK KQ))3__OBJSTORE__/HierarchicalDesign/HDProject/HDProjectPK ^:__OBJSTORE__/HierarchicalDesign/HDProject/HDProject_StrTbl/scs_2001PK __OBJSTORE__/PnAutoRun/PK __OBJSTORE__/PnAutoRun/Scripts/PK >*__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tclPK 髭1__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl_StrTblnamespace eval xilinx { namespace eval Dpm { proc GetIseVersion {} { set fsetName "fileset.txt" set fsetPath "" # Find the file in the Xilinx environment. # First, construct the environment path. set sep ":"; # Default to UNIX style seperator. if {[string compare -length 7 $::tcl_platform(platform) "windows"] == 0} { set sep ";"; # Platform is a Windows variant, so use semi-colon. } set xilinxPath $::env(XILINX) if [info exists ::env(MYXILINX)] then { set xilinxPath [join [list $::env(MYXILINX) $xilinxPath] $sep] } # Now look in each path of the path until we find a match. foreach xilElem [split $xilinxPath $sep] { set checkPath ${xilElem}/$fsetName set checkPath [ string map { \\ / } $checkPath ] if { [file exists $checkPath] } { set fsetPath $checkPath break } } if { [string equal $fsetPath ""] } { puts "ERROR: Can not determine the ISE software version." return "" } if { [catch { open $fsetPath r } fset] } { puts "ERROR: Could not open $fsetPath: $fset" return "" } # have the file open, scan for the version entry. set sVersion "" while { ![eof $fset] } { set line [gets $fset] regexp {version=(.*)} $line match sVersion # The above doesn't stop looking in the file. This assumes that if # there are multiple version entries, the last one is the one we want. } close $fset return $sVersion } proc CheckForIron {project_name} { # Determine if the currently running version of ProjNav is earlier than Jade. set version [GetIseVersion] set dotLocation [string first "." $version] set versionBase [string range $version 0 [expr {$dotLocation - 1}]] if {$versionBase < 9} { # The project file is newer than Iron, so take action to prevent the # file from being corrupted. # Make the file read-only. if {[string compare -length 7 $::tcl_platform(platform) "windows"]} { # The above will return 0 for a match to "windows" or "windows64". # This is the non-zero part of the if, for lin and sol. # Change the permissions to turn off writability. file attributes $project_name -permissions a-w } else { # On Windows, set file to read-only. file attributes $project_name -readonly 1 } # And tell the user about it. set messageText "WARNING: This project was last saved with a newer version of Project Navigator.\nThe project file will be made read-only so that it will not be invalidated by this version." # In the console window puts $messageText # And with a GUI message box if possible. ::xilinx::Dpm::TOE::loadGuiLibraries set iInterface 0 set messageDisplay 0 if {[catch { set iInterface [Xilinx::CitP::GetInstance $::xilinx::GuiI::IMessageDlgID] set messageDisplay [$iInterface GetInterface $::xilinx::GuiI::IMessageDlgID] if {$messageDisplay != 0} { # Managed to get a component to display a dialog, so use it set messageTitle "Incompatible Project Version (Newer)" set messageType 2 # 2 corresponds to a warning dialog. TclWrapGuiI_Init.cpp doesn't put the enum into Tcl. set messageTimeout 300000 # in milliseconds, 5 minutes set messageReturn [$messageDisplay MessageDlg $messageTitle $messageText $messageType 1 1 $messageTimeout "OK" "" ""] } } catchResult]} { # There was an error, probably because we aren't in a GUI enviroment. } else { # All is well. } set messageDisplay 0 set iInterface 0 } return 1 } } } ::xilinx::Dpm::CheckForIronPK __OBJSTORE__/ProjectNavigator/PK /__OBJSTORE__/ProjectNavigator/dpm_project_main/PK /RR?__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main H6PK '//F__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main_StrTblscs_2000spartan3acr2xbrvirtex2pPK &XX5__OBJSTORE__/ProjectNavigator/__stored_object_table__EV>MN\OVP [Qh&Ob<&MRݬHSOMOT{Q5UPnV]QWEQ}SXM=XQYHZW[(QI\eXU4PZ}QFU%\HQT~9XKpR&O_TESUuNX~YT:S)I+ZNY>JXqSTvY+SYJLQ=uUiQVON@EX=ErXEYMN\Uw6X/X PU]EDM7Q#RTx]ظXBcQm{QxU(]tZ]lX6{7Oe2MQy\Y=M:QO^BOwV'[FtXX4X9]`YA{StX)X+;Q:^64TR]Y#8O:YXQ(W\?]IXxqT\\~5TUxk`MS.<\cY!X8X(Q+*Na^XcU XdXOMkS$cT9OmoR7:MեXOG^ɔSvXd MO40Q9^[ͼUzQ0UXAL3X;QSe^_nEQhSwVWZWMM![*Q8zOtY(zXJhLTM^PrWX].X]ZqYPY>PEMNX\CMՓ#MVZ=RX~DXR^Q^mQCoZZ͍ZlQIkR[8\)AXX3FU=P U&4X:jXxQWE]4,Y8ZYNG_isW%ZUTtt^ӐSSU4\SQQq`rDT_qaM ]^mTsX2~WP QUYU'SWbMqQeU]Q@Y[:UK\X=Y]LsaޱXZ\Y1XgT.[X|c3Q1K|XvSKm[QkbNP JQ,}[ Y]b(bbY\@"M}YXwkSBQhYQ\`XhtRސb2PQ([bTVK[ЮbdDSa!^UMY*P eT4?~XsQaZQQR2xUES#uXlSd)QYW;b3sXjOBXi0VXS{ ZSP 3]-M} ]WX@ RP K] Q^=YXRVTa)RQMP ZXyer@ZũQ!C;TWo X]TXA^Y\EU]ۆ3TJT!M|SEOBMՕXTY?RY%\VQX)ZN^MOHM0QUKMXIXa7RիSHRqN;MգQTyTR^]7\:Q7T X NX"M?mRSU[MXjtOXXY$UU'2N;U&POE^YUhPXUY5ZS3XeCNNm[X'Q!}bFP MO&p\}`O.X%k]܉PKfX5 f(Xx}Xv]X|_XNY.. ^jmYuXFS9T6XMXX}y[6YZ\|"XU?+VPSM$TXXzYKQ[bwWQ$RYOP eITVbO%\b4a;X/{WaVIW?YwXt)Q+ Q2\N$^XMKY=yU\f\yMR2XY`=@Z3QJHTP HMX)MY^XwX$MX$Y!!MQUP$U7^U,ZKX$=QH\1V:Y:XP M,Qc Uv]vWNT|7XW1eo@MՙIMՇ.Y8gi7[XMO.[b4X^\SXAMSlT N\ pVhk9kT#)O{,V \jQpwQWYhrbcP[\,P gP PCX$Y~DYU#uQ0nQXNQP Y9z\EQ$ej)^Y \Y@RemH^˰V<kY8Se2(Y2XfnRilsQt~Xv^ObFgRXXY]WPR!Xb@igY=M՟ X9T\Ke-Y]vX>VT^UmIXQ52X1[MY,iR]jT&QJIHMՉXPRX7O{gS)Xz[_YMAQ-DPtXuj]MIzOXX-cfO)tXGge&[Y` MXL\#SE#^ZhYn[, [|Q_QM^Y@a3OYU+Y~"ZaQAoY3P `NMYJ1X<1WNS|*KMՃRM}X]io,OKmMM|)Y7XbYB]MXVXS N2 NXO{2V UYTiUadNI Q3#UQ+P<R)ZWO\ET*S,M#Mi\KT<VRUXy& XcydXc]k]]SPOjcXg_pQQ>oYO4T_l(\xdiqP =Y;5bcCT7X ATDXUUA[\GQPYS!Y!3XeXD%U8@M5U[@YT(S7~Q.r"XbMQ-SX\>XSMY/BZY$BTM\YXwgUZWT\XMZ}Y[MXPO\j[] Q^XXTTu;NlPY&9MէV"Mb6P WMf_q MnThmBQfXZS[ Y"Q2_tNX,RY?>y]OSGMՋObPDpYDY\.bL]SX}WEX-\TMCX>sOX$ZQLYXC-Q8XTCM9U1bLG]i6XCM,^Q)DMՑ~Q&1R2'Sb<X#1^DQJYH\=,N}YXO#YyAM՗]X0<v]PP dXDXP QZtX-^.V DRܩX3/^pQ\4\=X_rX(Fb5Y~Zc]TKbQmqXYTYRsjX&YQXK~"^B@TyMCSyQMSWXWx>SkR3^QgPNAXGNP rYDOQRֳQ%6\e**NM{%\PkXrO_aM~8XP[/]ڴ/`dMS&pR^̊\YY_UN Y"-XfT1lDVSmX'WyS#QR7ZYrV`XXJS=4;X9S:YSxH],Q:]OeN\MdT7ZPiQpZ=XW-VP mQ[PX]S[SOyX1WUHrSzX\$KXolb6#ZY/YInO[F5U:9FMՍXQkX4P\P@S]XbG.=T_MNo_s$Q6TpRU(MzX[\\U_AvXu%S,$XwW ^ǚMv'MX>\YRXIO3]M%X=OkYr0XhR(Q&[d!MVPXP |uXuSRߜ_NXX*XyS!Z{YP jY'LWCVWU`TBzRfaT?Q#J]v*^=UxO[VX@\N8O#XI:S_aP S1QM+^<QeOvU))QPQ*iRP \,~W;WP -SYTVdXR٠I`iobT< Z Q4X/cM.^ UOH])XLpQw b3GlYiX,5U.-Qd\QS_llnR'X!3R<X b2[t!XJWe:_e\MOaQVCQjO$EMՏ[l%^wXFiiS4YYiRPTzUO\Q6\U_k[P ZEP QW`_n`MX61V ]yQ('ZVXXQXY; ^IQOY KXY[lgg(MWY4XN(e\!gXBQGprQrPS[V_kR<\ XX"?T+QcXs]P XxGTAXUM"~QFFQXYS4JXX`U:TxUt]zXXXiT(O1yWuQSjcXwgXNN~MNUjCT\@]݌eXY}]X[Π R&\7vuWM\wN#X7/YQ`P 6w]0[S@ 6\s\sZi\BP MU UN]hp1PSQ?W'[]=MYakqQDFRRUy`Q<MաW[D OY-P.PQ"q'O7~5MX5Q?OZO@ RdLXlP5i[IO=4A_gO,$RUP XrY'^D_h@6MXX~oTaYQ\&hV8MթUVmQSY Y]XfRSN@LYwhRTMrQO)IY)(^xWP R\Y"XZCZX>Y[XDaXhT+^\zQbX:w\wXEQKqQLMՁM?fXCMnYCUHQiJ9X|XOMU]{SQ'M[PY-h_pO O|*[,RX|;aSF]XVM ^SQQSSV4VrQR]jS\QZ0]1XgX{bMTU}H/Q95RRebOX5P |XXX{XX|ioQD&^sQE4y\tYGP0W kit41XYW0V PvGOQX[lPbI])OO ^\NFJMՅ [U| P PoV?8Tkx[=]N Q6KQ$)Qb8S{\_Y?Q<eVX],[JQN\vX!bOFWPXPbM XQIMlR"X8&YHZTSQ]X{Cihn_sh*ZvXFeXRM&VCS}hSYP YSGXrQ/QQ^TH&#UbTdWYY$qYvLX+:XpQDa_nbG>Q;yXv0QI:MR\>T[Q[QZ4X{4Q~U ][rd[bKe_qdP  Q]>M՝lYC+AQ<V[WXz- kԣrY0YW^[TPKVXP 8XRQam_sXVPM ^ц]);MP.]OxXbcQB[Y% NZ?M՛XaM B[bXTBXRXkMVs`s lBJGXBϿ&ZȃL*%bE⧋_Z_Q0Cg|EKTw38JsvG78?Z{9"vIų@tI;glWJdNތwo-J1JRD[Yb"Lۋ8o#*KۧegC4M;{qH%峀5#dt@w?9h :DN)A9@p0E=apN4+>ƶ$Eȝ/tC#G^U% >JuN n.i__;O.qt^Mo\ \c♴L%HWLEI[ᯚ@TOX AwEN(Bm(0JҢ_ħsJmLJ欽9]A9I^OoAV>tX⃥sM $L0H۞|6@Ӫ㰗 FȂ*z6.}wB1G\, Ju4(ֈʸ:4Jڅ#a-OFĖpvzhwN|i#{?Hq"]uG. aP]*zI⾁-)FuTF@ĕM&`)wwbIܬ15wǐ%Ej# u wC*DɬNHH}HE/B&{x1YK5|DEwUkyKBl2>;%k4xE#[5P\|uDz5).[9L5 'WVKOu͟#^>fcH. `.(υ8NDIAH'DM@?Loi(JxH(A"r1K)o)o/ZYKٺc u,iLGK 9v͔D޸ ן| BwQB:5X?hCHM~-ђpJĮp($FFy EkLԽkAPO^.0 ӬM6~0Q NJ\LW=YB2.HÛGۺ!4; a&ISWa>^}Ov7h/M5/Z-9Bpݩ@{ *J->u_f+ITބ};/7DF´?JLTIuDUJ8z.IR.*@{|r0Dױx}^8ˠNi s~V\Fq_IЊTCM~>?O >K7z:SO\AūTl XHI=f# 0c+lnDrEJg؂Z?Hwyl@Mv O۪x =I_ߣ#*fOCݻ>zU:~AuS'}E; {,O܃O?dʛa6cM#;]岮OsU1(U5+I3/8NLXBV/Y(vɷ4LTH'چpCBݕq(LUH~r(a`sH(?܌LyAL?ۉ3WxvGzF-BBҕf W8pIc(yGE/GN%؜GIG*1IWԂĚ")˜)AڪI\A5]Oq4`E9NQ3F씽a1aH@32E s0}.BP27bL)7q7a_MǴrm^h&oM9,yqDQ-0/Nخ< ".I+'m+[) ,MfJMhJ) D@qlCOof{W'8ԽESXq}{cO T[p J g.h@Ѷ+kB M̽,G3|AHL#gAk'M&MȢ>{@] @ADžЃNL@J<-#YoJo0jCzx|%o@!sJ/M:̒v A&@ }ڳl^/G864fԤD̲='xFVS|>MH~H^it&Lz=¿!'s F %cE1Ϊ)Hl >ѧjdp]$Io$nrHc gNzUSQf K/CHkI3kJ\ B<1>7@9\jxG}F{`ae(urE'͠zKH@iWq]H{~cPDp$Bc9C'lHŤH2S";Ej&4Aml@O Y48LDCX& 5+GOEs`̇@3? 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UT_LST|File||C:/midas/mscb/embedded/scs_2001/cpld/scs_2000.bld|PLUGIN_General|0||File||C:/midas/mscb/embedded/scs_2001/cpld/scs_2000.ngd|PLUGIN_NGD|0||File||C:/midas/mscb/embedded/scs_2001/cpld/scs_2000.cmd_log|PLUGIN_General|0||File||C:/midas/mscb/embedded/scs_2001/cpld/scs_2000.ngr|PLUGIN_NGR|0||File||C:/midas/mscb/embedded/scs_2001/cpld/scs_2000.ngc|PLUGIN_NGC|0||File||C:/midas/mscb/embedded/scs_2001/cpld/xst|PLUGIN_General|1305021309||Generic||xstxst|File||C:/midas/mscb/embedded/scs_2001/cpld/scs_2000.syr|PLUGIN_General|0||File||C:/midas/mscb/embedded/scs_2001/cpld/scs_2000.lso|PLUGIN_General|0||File||C:/midas/mscb/embedded/scs_2001/cpld/scs_2000.xst|PLUGIN_General|0||File||C:/midas/mscb/embedded/scs_2001/cpld/scs_2000.prj|PLUGIN_General|0|AutoGeneratedViewVIEW_Post-TranslateFloorplanDesignTBIND_FloorplanDesignTRAN_floorplanDesignVIEW_TranslationTBIND_NGCAssignPackagePinsTRAN_ngcAssignPackagePinsVIEW_ngcAssignPackagePinsTBIND_CreateTimingConstraintsTRAN_createTimingConstraintsVIEW_Post-TranslateTimingConstraintsTBIND_CreateAreaConstraintsTRAN_createAreaConstraintsVIEW_Post-TranslateAreaConstraintsTBINDEXT_TranslationToFit_xbrLowDefaulttrue-7XST (VHDL/Verilog)ISE Simulator (VHDL/Verilog)Always32Keeperscs_2001_timesim.v28DensitySourceFastxc2c384LVCMOS33VerilogTQ144NoneOptimize DensityHDLSummary38GroundTRANEXT_vm6File_xbrVIEW_FitTBIND_FitToPost-FitAbstractSimulationTRAN_postFitSimModelVIEW_Post-FitAbstractSimulationTBIND_Post-FitAbstractToTBWPreSimulationTRAN_createPostFitTestBenchTRAN_copyPost-FitAbstractToPreSimulationVIEW_TBWPost-FitPreSimulationTBIND_TBWPost-FitPreToFuseTRAN_ISimulatePostFitModelRunFuse(bencher)VIEW_TBWPost-FitFuseTBIND_TBWPost-FitFuseToSimulationISimTRAN_ISimulatePostFitModel(bencher)VIEW_TBWPost-FitSimulationISimTBIND_Post-FitAbstractToPreSimulationVIEW_Post-FitPreSimulationTBIND_Post-FitPreToFuseTRAN_ISimulatePostFitModelRunFuseVIEW_Post-FitFuseTBIND_Post-FitFuseToSimulationISimTRAN_ISimulatePostFitModelVIEW_Post-FitSimulationISimTBIND_FitToLockedPinConstraintsCPLDTRAN_lockPinsVIEW_LockedPinConstraintsCPLDTBIND_FitToCPLDGenerateTimingTRAN_timRptVIEW_CPLDGenerateTimingTBINDEXT_genPowerData_xpla3TRANEXT_genPowerData_xpla3VIEW_CPLDGeneratePowerDataTBINDEXT_createIBISModel_xbrTRANEXT_createIBISModel_xbrVIEW_IBISModelTBINDEXT_XPower_xpla3TRANEXT_XPower_xpla3VIEW_CPLDAnalyzePowerTBINDEXT_FitToCPLDConfiguration_xbrTRANEXT_crtProg_xbrVIEW_CPLDConfigurationTBIND_CPLDConfigurationToCPLDConfigureTargetDeviceTRAN_configureTargetDevice_CPLDVIEW_CPLDConfigureTargetDeviceTBIND_CPLDConfigurationToCPLDConfigureDeviceTRAN_impactProgrammingTool_CPLDVIEW_CPLDConfigureDeviceTBIND_StructuralToTranslationTRAN_ngdbuildVIEW_StructuralTBINDEXT_XSTPreSynthesisToStructural_xbrArchitecture|scs_2001|BehavioralTRAN_compileBCD2YesArea<>AutoAs OptimizedHighNo_Maintain./xstTRANEXT_xstsynthesize_xbrVIEW_XSTPreSynthesisTBIND_XSTAssignPackagePinsTRAN_assignPackagePinsVIEW_AssignPackagePinsTBIND_CPLDXSTAbstractToPreSynthesisTRAN_convertToHdlTRAN_copyAbstractToPreSynthesisForSynthesisVIEW_CPLDXSTAbstractSynthesis/scs_2001TBIND_InitialToCPLDXSTAbstractSynthesisTRAN_copyInitialToXSTAbstractSynthesisVIEW_InitialTBIND_InitialToCPLDAbstractSimulationTRAN_copyInitialToAbstractSimulationVIEW_CPLDAbstractSimulationTBIND_CPLDAbstractToPostAbstractSimulationTRAN_copyAbstractToPostAbstractSimulationVIEW_PostAbstractSimulationTBIND_PostAbstractToTBWPreSimulationTRAN_viewBehavioralTestbenchTRAN_copyPostAbstractToPreSimulationVIEW_TBWPreSimulationTBIND_TBWPreToBehavioralFuseTRAN_ISimulateBehavioralModelRunFuse(bencher)VIEW_TBWBehavioralFuseTBIND_TBWBehavioralFuseToSimulationISimTRAN_ISimulateBehavioralModel(bencher)VIEW_TBWBehavioralSimulationISimTBIND_PostAbstractToPreSimulationVIEW_PreSimulationTBIND_PreToBehavioralFuseTRAN_ISimulateBehavioralModelRunFuseVIEW_BehavioralFuseTBIND_BehavioralFuseToSimulationISimTRAN_ISimulateBehavioralModelVIEW_BehavioralSimulationISimTBIND_PostAbstractToAnnotatedPreSimulationTRAN_viewBehavioralTestbenchForAnnoTRAN_copyPostAbstractToAnnotatedPreSimulationVIEW_AnnotatedPreSimulationTBIND_PreToGenerateAnnotatedResultsFuseTRAN_ISimGenerateAnnotatedResultsRunFuseTRAN_copyPreToGenerateAnnotatedResultsFuseForTBWVIEW_AnnotatedResultsFuseTBIND_FuseToAnnotatedResultsISimTRAN_ISimGenerateAnnotatedResultsTRAN_copyFuseToAnnotatedResultsISimForTBWVIEW_AnnotatedResultsISimTBIND_AnnotatedToGenerateExpectedSimulationResultsISimTRAN_ISimGenerateExpectedSimulationResultsVIEW_ExpectedSimulationResultsISimTBINDEXT_InitialToCommon_CPLDTRANEXT_compLibraries_CPLDVIEW_CommonDESPF_TRADITIONALPROP_PreferredLanguagePROP_SimulatorOther MixedOther VerilogOther VHDLVCS-MXi MixedVCS-MXi VerilogVCS-MXi VHDLVCS-MX MixedVCS-MX VerilogVCS-MX VHDLNC-Sim MixedNC-Sim VerilogNC-Sim VHDLModelsim-XE VerilogModelsim-XE VHDLModelsim-PE MixedModelsim-PE VerilogModelsim-PE VHDLModelsim-SE MixedModelsim-SE VerilogModelsim-SE VHDLPROP_Synthesis_ToolPROP_Top_Level_Module_TypeXST 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(*)|*PROP_ISimLibSearchOrderFilePROP_isimSpecifyDefMacroAndValuePROP_isimSpecifySearchDirectoryPROP_isimValueRangeCheckPROP_ISimSDFTimingToBeReadSetup TimePROP_ISimVCDFileName_par_tbwxpower.vcdPROP_ISimGenVCDFile_par_tbwPROP_ISimUseCustomSimCmdFile_par_tbwPROP_ISimVCDFileName_par_tbPROP_ISimGenVCDFile_par_tbPROP_ISimUseCustomSimCmdFile_par_tbPROP_ISimSimulationRunTime_behav_tbw1000 nsPROP_ISimSimulationRun_behav_tbwPROP_ISimUseCustomSimCmdFile_behav_tbwPROP_ISimSimulationRunTime_behav_tbPROP_ISimSimulationRun_behav_tbPROP_ISimUseCustomSimCmdFile_behav_tbPROP_ISimSimulationRunTime_par_tbwPROP_ISimSimulationRun_par_tbwPROP_ISimSimulationRunTime_par_tbPROP_ISimSimulationRun_par_tbPROP_isimCompileForHdlDebugPROP_isimIncreCompilationPROP_ISimCustomSimCmdFileName_gen_tbwPROP_ISimUseCustomSimCmdFile_gen_tbwPROP_ISimCustomSimCmdFileName_behav_tbwPROP_ISimCustomSimCmdFileName_behav_tbPROP_ISimCustomSimCmdFileName_par_tbwPROP_ISimCustomSimCmdFileName_par_tbPROP_ISimUutInstNameUUTPROP_xstEquivRegRemovalPROP_xilxSynthAddIObufPROP_SynthExtractMuxPROP_SynthResSharingPROP_SynthCaseImplStylePROP_xstBusDelimiterPROP_xstHierarchySeparatorPROP_xstGenerateRTLNetlistPROP_xst_otherCmdLineOptionsPROP_xstVerilogMacrosPROP_xstGenericsParametersPROP_xstUserCompileListPROP_xstVerilog2001PROP_xstIniFilePROP_xstWorkDirPROP_xstCasePROP_xstLibSearchOrderPROP_xstUseSynthConstFilePROP_SynthConstraintsFileCST files (*.cst)|*.cstXCF files (*.xcf)|*.xcfPROP_SynthOptEffortPROP_SynthOptPROP_xmpInstTempTargetLangPROP_coregenFuncModelTargetLangPROP_bencherPostParTestbenchNamePROP_tbwTestbenchTargetLangPROP_PostParSimTopPROP_xawHdlSourceTargetLangPROP_netgenPostParSimModelNamePROP_SynthTopPROP_SimModelNoEscapeSignalPROP_SimModelPathUsedInSdfAnnPROP_SimModelIncSdfAnnInVerilogFilePROP_SimModelIncUselibDirInVerilogFilePROP_SimModelRenTopLevModPROP_SimModelOtherNetgenOptsPROP_SimModelOutputExtIdentPROP_SimModelGenArchOnlyPROP_SimModelRenTopLevInstToPROP_SimModelGenerateTestbenchFilePROP_SimModelRenTopLevArchToStructurePROP_netgenRenameTopLevEntToPROP_SimModelRocPulseWidthPROP_SimModelBringOutGsrNetAsAPortPROP_SimModelGsrPortNameGSR_PORTPROP_CompxlibSimPrimativesPROP_CompxlibUniSimLibPROP_CompxlibOtherCompxlibOptsPROP_CompxlibOverwriteLibOverwritePROP_CompxlibSimPathSearch in PathPROP_CompxlibOutputDir$XILINX//PROP_xawInstTempTargetLangPROP_hdlInstTempTargetLangPROP_schInstTempTargetLangPROP_schFuncModelTargetLangPROP_DesignNamePROP_PartitionForceSynthPROP_PartitionCreateDeletePROP_SmartGuideFileNamescs_2001_guide.ncdPROP_UseSmartGuideNCD files (*.ncd)|*.ncdPROP_PostFitSimTopPROP_BehavioralSimTopPROP_SteCreatedByPK !__OBJSTORE__/ProjectNavigatorGui/PK xl/__OBJSTORE__/ProjectNavigatorGui/GuiProjectData PK 36__OBJSTORE__/ProjectNavigatorGui/GuiProjectData_StrTblArchitecture|scs_2001|Behavioralscs_2001 - Behavioral (scs_2001.vhd)xc2c384-7TQ144scs_2001Design UtilitiesDESUT_UCFUser ConstraintsDESUT_VHDL_ARCHITECTUREImplement DesignImplement Design/Configure Target DeviceImplement Design/FitImplement Design/Optional Implementation ToolsImplement Design/Synthesize - XSTImplement Design/TranslateDESUT_VHDL_PACKAGE_DECLXilinx ISE SimulatorPK __OBJSTORE__/STE/PK __OBJSTORE__/SrcCtrl/PK "__OBJSTORE__/SrcCtrl/SavedOptions/PK __OBJSTORE__/_ProjRepoInternal_/PK __OBJSTORE__/common/PK '__OBJSTORE__/common/HierarchicalDesign/PK KQ))0__OBJSTORE__/common/HierarchicalDesign/HDProjectPK (Ts7__OBJSTORE__/common/HierarchicalDesign/HDProject_StrTblscs_2001PK __REGISTRY__/PK __REGISTRY__/Autonym/PK __REGISTRY__/Autonym/regkeysPK __REGISTRY__/Cs/PK __REGISTRY__/Cs/regkeysPK __REGISTRY__/HierarchicalDesign/PK *__REGISTRY__/HierarchicalDesign/HDProject/PK XR1__REGISTRY__/HierarchicalDesign/HDProject/regkeysCommandLine-Map s CommandLine-Ngdbuild s CommandLine-Par s CommandLine-Xst s Previous-NGD s Previous-NGM s Previous-Packed-NCD s Previous-Routed-NCD s PK '__REGISTRY__/HierarchicalDesign/regkeysPK __REGISTRY__/ProjectNavigator/PK \uDD%__REGISTRY__/ProjectNavigator/regkeysISE_VERSION_LAST_SAVED_WITH 10.1.03 s sMigrationTypeKey reconcile s PK !__REGISTRY__/ProjectNavigatorGui/PK (__REGISTRY__/ProjectNavigatorGui/regkeysPK __REGISTRY__/ProjectSeedData/PK /__REGISTRY__/ProjectSeedData/ProcessProperties/PK \<,<,6__REGISTRY__/ProjectSeedData/ProcessProperties/regkeysNUM_PROPERTIES 176 s prop_100_name PROP_xilxSynthXORPreserve s prop_100_val "true" s prop_101_name PROP_xilxSynthKeepHierarchy_CPLD s prop_101_val "Yes" s prop_102_name PROP_PlsClockEnable s prop_102_val "true" s prop_103_name PROP_CompxlibAbelLib s prop_103_val "true" s prop_104_name PROP_CompxlibCPLDDetLib s prop_104_val "true" s prop_105_name PROP_xcpldFitTemplate_xpla3 s prop_105_val "Optimize Density" s prop_106_name PROP_FunctionBlockInputLimit s prop_106_val "38" s prop_107_name PROP_xcpldFitDesInputLmt_xbr s prop_107_val "32" s prop_108_name PROP_xcpldFitDesUnused s prop_108_val "Ground" s prop_109_name PROP_xcpldFitDesTriMode s prop_109_val "Keeper" s prop_10_name PROP_PartitionForceSynth s prop_10_val "" s prop_110_name PROP_xcpldFitDesVolt s prop_110_val "LVCMOS33" s prop_111_name PROP_UseDataGate s prop_111_val "true" s prop_112_name PROP_xilxBitgCfg_GenOpt_IEEE1532File_xbr s prop_112_val "false" s prop_113_name PROP_DevFamily s prop_113_val "CoolRunner2 CPLDs" s prop_114_name PROP_Simulator s prop_114_val "ISE Simulator (VHDL/Verilog)" s prop_115_name PROP_SmartGuideFileName s prop_115_val "scs_2001_guide.ncd" s prop_116_name PROP_SimModelRenTopLevInstTo s prop_116_val "UUT" s prop_117_name PROP_SynthConstraintsFile s prop_117_val "" s prop_118_name PROP_ISimCustomSimCmdFileName_par_tb s prop_118_val "" s prop_119_name PROP_ISimCustomSimCmdFileName_par_tbw s prop_119_val "" s prop_11_name PROP_DesignName s prop_11_val "scs_2000" s prop_120_name PROP_ISimCustomSimCmdFileName_behav_tb s prop_120_val "" s prop_121_name PROP_ISimCustomSimCmdFileName_behav_tbw s prop_121_val "" s prop_122_name PROP_ISimCustomSimCmdFileName_gen_tbw s prop_122_val "" s prop_123_name PROP_ISimSimulationRun_par_tb s prop_123_val "true" s prop_124_name PROP_ISimSimulationRun_par_tbw s prop_124_val "true" s prop_125_name PROP_ISimSimulationRun_behav_tb s prop_125_val "true" s prop_126_name PROP_ISimSimulationRun_behav_tbw s prop_126_val "true" s prop_127_name PROP_ISimGenVCDFile_par_tb s prop_127_val "false" s prop_128_name PROP_ISimGenVCDFile_par_tbw s prop_128_val "false" s prop_129_name PROP_ISimCustomCompilationOrderFile s prop_129_val "" s prop_12_name PROP_Dummy s prop_12_val "dum1" s prop_130_name PROP_impactBaud s prop_130_val "None" s prop_131_name PROP_impactPort s prop_131_val "Auto - default" s prop_132_name PROP_XPowerOptMaxNumberLines s prop_132_val "1000" s prop_133_name PROP_xstSafeImplement s prop_133_val "No" s prop_134_name PROP_FitterOptimization_xpla3 s prop_134_val "Density" s prop_135_name PROP_xcpldFitDesPtermLmt_xbr s prop_135_val "28" s prop_136_name PROP_xcpldFitDesInReg_xbr s prop_136_val "true" s prop_137_name PROP_DevFamilyPMName s prop_137_val "xbr" s prop_138_name PROP_DevDevice s prop_138_val "xc2c384" s prop_139_name PROP_CompxlibSimPath s prop_139_val "Search in Path" s prop_13_name PROP_CompxlibOutputDir s prop_13_val "$XILINX//" s prop_140_name PROP_CompxlibLang s prop_140_val "VHDL" s prop_141_name PROP_SimModelGenMultiHierFile s prop_141_val "false" s prop_142_name PROP_ISimSimulationRunTime_par_tb s prop_142_val "1000 ns" s prop_143_name PROP_ISimSimulationRunTime_par_tbw s prop_143_val "1000 ns" s prop_144_name PROP_ISimSimulationRunTime_behav_tb s prop_144_val "1000 ns" s prop_145_name PROP_ISimSimulationRunTime_behav_tbw s prop_145_val "1000 ns" s prop_146_name PROP_ISimVCDFileName_par_tb s prop_146_val "xpower.vcd" s prop_147_name PROP_ISimVCDFileName_par_tbw s prop_147_val "xpower.vcd" s prop_148_name PROP_DevPackage s prop_148_val "TQ144" s prop_149_name PROP_Synthesis_Tool s prop_149_val "XST (VHDL/Verilog)" s prop_14_name PROP_CompxlibOverwriteLib s prop_14_val "Overwrite" s prop_150_name PROP_CompxlibUniSimLib s prop_150_val "true" s prop_151_name PROP_CompxlibUni9000Lib s prop_151_val "true" s prop_152_name PROP_DevSpeed s prop_152_val "-7" s prop_153_name PROP_PreferredLanguage s prop_153_val "Verilog" s prop_154_name PROP_schFuncModelTargetLang s prop_154_val "VHDL" s prop_155_name PROP_schInstTempTargetLang s prop_155_val "VHDL" s prop_156_name PROP_hdlInstTempTargetLang s prop_156_val "VHDL" s prop_157_name PROP_xawInstTempTargetLang s prop_157_val "VHDL" s prop_158_name PROP_SimModelTarget s prop_158_val "Verilog" s prop_159_name PROP_xawHdlSourceTargetLang s prop_159_val "VHDL" s prop_15_name PROP_CompxlibOtherCompxlibOpts s prop_15_val "" s prop_160_name PROP_tbwTestbenchTargetLang s prop_160_val "Verilog" s prop_161_name PROP_coregenFuncModelTargetLang s prop_161_val "VHDL" s prop_162_name PROP_xmpInstTempTargetLang s prop_162_val "Verilog" s prop_163_name PROP_SimModelRenTopLevArchTo s prop_163_val "Structure" s prop_164_name PROP_SimModelGenArchOnly s prop_164_val "false" s prop_165_name PROP_SimModelOutputExtIdent s prop_165_val "false" s prop_166_name PROP_SimModelRenTopLevMod s prop_166_val "" s prop_167_name PROP_SimModelIncUselibDirInVerilogFile s prop_167_val "false" s prop_168_name PROP_SimModelIncSdfAnnInVerilogFile s prop_168_val "true" s prop_169_name PROP_SimModelNoEscapeSignal s prop_169_val "false" s prop_16_name PROP_CompxlibSimPrimatives s prop_16_val "true" s prop_170_name PROP_netgenPostParSimModelName s prop_170_val "scs_2001_timesim.v" s prop_171_name PROP_bencherPostParTestbenchName s prop_171_val "" s prop_172_name PROP_SimModelIncSimprimInVerilogFile s prop_172_val "false" s prop_173_name PROP_SimModelAutoInsertGlblModuleInNetlist s prop_173_val "true" s prop_174_name PROP_SimModelBringOutGsrNetAsAPort s prop_174_val "false" s prop_175_name PROP_netgenRenameTopLevEntTo s prop_175_val "" s prop_176_name PROP_SimModelPathUsedInSdfAnn s prop_176_val "Default" s prop_17_name PROP_SimModelGenerateTestbenchFile s prop_17_val "false" s prop_18_name PROP_SimModelOtherNetgenOpts s prop_18_val "" s prop_19_name PROP_SimModelRetainHierarchy s prop_19_val "true" s prop_1_name PROP_SteCreatedBy s prop_1_val "" s prop_20_name PROP_SynthOpt s prop_20_val "Area" s prop_21_name PROP_SynthOptEffort s prop_21_val "High" s prop_22_name PROP_xstUseSynthConstFile s prop_22_val "true" s prop_23_name PROP_xstLibSearchOrder s prop_23_val "" s prop_24_name PROP_xstCase s prop_24_val "Maintain" s prop_25_name PROP_xstWorkDir s prop_25_val "./xst" s prop_26_name PROP_xstIniFile s prop_26_val "" s prop_27_name PROP_xstVerilog2001 s prop_27_val "true" s prop_28_name PROP_xstVeriIncludeDir_Global s prop_28_val "" s prop_29_name PROP_xstUserCompileList s prop_29_val "" s prop_2_name PROP_Parse_Target s prop_2_val "synthesis" s prop_30_name PROP_xstGenericsParameters s prop_30_val "" s prop_31_name PROP_xstVerilogMacros s prop_31_val "" s prop_32_name PROP_xst_otherCmdLineOptions s prop_32_val "" s prop_33_name PROP_xstGenerateRTLNetlist s prop_33_val "Yes" s prop_34_name PROP_xstHierarchySeparator s prop_34_val "_" s prop_35_name PROP_xstBusDelimiter s prop_35_val "<>" s prop_36_name PROP_SynthFsmEncode s prop_36_val "Auto" s prop_37_name PROP_SynthCaseImplStyle s prop_37_val "None" s prop_38_name PROP_SynthResSharing s prop_38_val "true" s prop_39_name PROP_SynthExtractMux s prop_39_val "Yes" s prop_3_name PROP_Top_Level_Module_Type s prop_3_val "HDL" s prop_40_name PROP_xilxSynthAddIObuf s prop_40_val "true" s prop_41_name PROP_xstEquivRegRemoval s prop_41_val "true" s prop_42_name PROP_ISimUutInstName s prop_42_val "UUT" s prop_43_name PROP_ISimUseCustomSimCmdFile_par_tb s prop_43_val "false" s prop_44_name PROP_ISimUseCustomSimCmdFile_par_tbw s prop_44_val "false" s prop_45_name PROP_ISimUseCustomSimCmdFile_behav_tb s prop_45_val "false" s prop_46_name PROP_ISimUseCustomSimCmdFile_behav_tbw s prop_46_val "false" s prop_47_name PROP_ISimUseCustomSimCmdFile_gen_tbw s prop_47_val "false" s prop_48_name PROP_isimIncreCompilation s prop_48_val "true" s prop_49_name PROP_isimCompileForHdlDebug s prop_49_val "true" s prop_4_name PROP_SynthTop s prop_4_val "Architecture|scs_2001|Behavioral" s prop_50_name PROP_ISimSDFTimingToBeRead s prop_50_val "Setup Time" s prop_51_name PROP_isimValueRangeCheck s prop_51_val "false" s prop_52_name PROP_isimSpecifySearchDirectory s prop_52_val "" s prop_53_name PROP_isimSpecifyDefMacroAndValue s prop_53_val "" s prop_54_name PROP_ISimLibSearchOrderFile s prop_54_val "" s prop_55_name PROP_ISimUseCustomCompilationOrder s prop_55_val "false" s prop_56_name PROP_ISimOtherCompilerOptions_behav s prop_56_val "" s prop_57_name PROP_ISimOtherCompilerOptions_fit s prop_57_val "" s prop_58_name PROP_ibiswriterShowAllModels s prop_58_val "false" s prop_59_name PROP_ImpactProjectFile s prop_59_val "Default" s prop_5_name PROP_BehavioralSimTop s prop_5_val "Architecture|scs_2001|Behavioral" s prop_60_name PROP_ngdbuild_otherCmdLineOptions s prop_60_val "" s prop_61_name PROP_xilxNgdbld_AUL s prop_61_val "false" s prop_62_name PROP_xilxNgdbldMacro s prop_62_val "" s prop_63_name PROP_xilxSynthKeepHierarchy s prop_63_val "No" s prop_64_name PROP_xstNetlistHierarchy s prop_64_val "As Optimized" s prop_65_name PROP_XPowerOptVerboseRpt s prop_65_val "false" s prop_66_name PROP_XPowerOptLoadXMLFile s prop_66_val "Default" s prop_67_name PROP_XPowerOptOutputFile s prop_67_val "Default" s prop_68_name PROP_XPowerOptLoadVCDFile s prop_68_val "Default" s prop_69_name PROP_XPowerOptInputTclScript s prop_69_val "" s prop_6_name PROP_PostParSimTop s prop_6_val "" s prop_70_name PROP_XPowerOtherXPowerOpts s prop_70_val "" s prop_71_name PROP_XplorerMode s prop_71_val "Off" s prop_72_name PROP_UserEditorPreference s prop_72_val "ISE Text Editor" s prop_73_name PROP_UserEditorCustomSetting s prop_73_val "" s prop_74_name PROP_UserConstraintEditorPreference s prop_74_val "Constraints Editor" s prop_75_name PROP_FlowDebugLevel s prop_75_val "0" s prop_76_name PROP_FitterReportFormat s prop_76_val "HTML" s prop_77_name PROP_Enable_Message_Capture s prop_77_val "true" s prop_78_name PROP_Enable_Message_Filtering s prop_78_val "false" s prop_79_name PROP_Enable_Incremental_Messaging s prop_79_val "false" s prop_7_name PROP_PostFitSimTop s prop_7_val "" s prop_80_name PROP_lockPinsUcfFile s prop_80_val "" s prop_81_name PROP_EnableWYSIWYG s prop_81_val "None" s prop_82_name PROP_xcpldUseLocConst s prop_82_val "Always" s prop_83_name PROP_xcpldFitDesInit s prop_83_val "Low" s prop_84_name PROP_xcpldFitDesTimingCst s prop_84_val "true" s prop_85_name PROP_CPLDFitkeepio s prop_85_val "false" s prop_86_name PROP_cpldBestFit s prop_86_val "false" s prop_87_name PROP_xcpldFitDesMultiLogicOpt s prop_87_val "true" s prop_88_name PROP_cpldfit_otherCmdLineOptions s prop_88_val "" s prop_89_name PROP_fitGenSimModel s prop_89_val "false" s prop_8_name PROP_UseSmartGuide s prop_8_val "false" s prop_90_name PROP_cpldfitHDLeqStyle s prop_90_val "Source" s prop_91_name PROP_xcpldFitDesSlew s prop_91_val "Fast" s prop_92_name PROP_xcpldUseGlobalClocks s prop_92_val "true" s prop_93_name PROP_xcpldUseGlobalOutputEnables s prop_93_val "true" s prop_94_name PROP_xcpldUseGlobalSetReset s prop_94_val "true" s prop_95_name PROP_hprep6_autosig s prop_95_val "false" s prop_96_name PROP_hprep6_otherCmdLineOptions s prop_96_val "" s prop_97_name PROP_xcpldFittimRptOption s prop_97_val "Summary" s prop_98_name PROP_taengine_otherCmdLineOptions s prop_98_val "" s prop_99_name PROP_xilxSynthMacroPreserve s prop_99_val "true" s prop_9_name PROP_PartitionCreateDelete s prop_9_val "" s PK /__REGISTRY__/ProjectSeedData/ProjectProperties/PK $ss6__REGISTRY__/ProjectSeedData/ProjectProperties/regkeysPROP_DevDevice xc2c384 s PROP_DevFamily CoolRunner2 CPLDs s PROP_DevPackage TQ144 s PROP_DevSpeed -7 s PROP_Enable_Incremental_Messaging false s PROP_Enable_Message_Capture true s PROP_Enable_Message_Filtering false s PROP_PreferredLanguage Verilog s PROP_Simulator ISE Simulator (VHDL/Verilog) s PROP_Synthesis_Tool XST (VHDL/Verilog) s PROP_Top_Level_Module_Type HDL s PK +__REGISTRY__/ProjectSeedData/UserLibraries/PK K(2__REGISTRY__/ProjectSeedData/UserLibraries/regkeysNUM_USER_LIBRARIES 0 s PK ,__REGISTRY__/ProjectSeedData/UserPartitions/PK }W~`3__REGISTRY__/ProjectSeedData/UserPartitions/regkeysNUM_USER_PARTITIONS 0 s PK -__REGISTRY__/ProjectSeedData/UserSourceFiles/PK ĉii4__REGISTRY__/ProjectSeedData/UserSourceFiles/regkeysNUM_USER_FILES 3 s user_file_1 scs_2001.vhd s user_file_2 scs_2001_pack.vhd s user_file_3 scs_2001.ucf s PK $Id''$__REGISTRY__/ProjectSeedData/regkeysDATA_VERSION 1 s ISE_VERSION 10.1.03 s PK __REGISTRY__/STE/PK __REGISTRY__/STE/XSLTProcess/PK 齻{$__REGISTRY__/STE/XSLTProcess/regkeysCommandLine C:\Xilinx\10.1\ISE\bin\nt\unwrapped\XSLTProcess.exe -ise C:/midas/mscb/embedded/scs_2001/cpld/scs_2001.ise scs_2001_build.xml s FormatString xsltprocess [--intstyle ise|xflow|silent] [-a] [-w] [--libxslt ] s PK __REGISTRY__/STE/cpldfit/PK p E __REGISTRY__/STE/cpldfit/regkeysCommandLine C:\Xilinx\10.1\ISE\bin\nt\unwrapped\cpldfit.exe -ise C:/midas/mscb/embedded/scs_2001/cpld/scs_2001.ise -intstyle ise -p xc2c384-7-TQ144 -ofmt vhdl -optimize density -htmlrpt -loc on -slew fast -init low -inputs 32 -inreg on -blkfanin 38 -pterms 28 -unused ground -terminate keeper -iostd LVCMOS33 scs_2001.ngd s FormatString cpldfit [-p ] [-intstyle ise|xflow|silent] [-optimize density|speed] [--tspec_partition] [-nomlopt] [-ignoretspec] [-init low|high|fpga] [-slew fast|slow|auto] [-loc on|off|try] [-log ] [-wysiwyg] [-keepio] [--opt_xxx] [--opt_yyy] [--opt_zzz] [--xplaopt_verify] [-ofmt abel|vhdl|verilog] [-exhaust] [-inputs ] [-pterms ] [-inreg on|off] [--old_speed] [--nobufropt] [-nogclkopt] [-nogsropt] [-nogtsopt] [-ignoredatagate] [-unused ground|pullup|keeper|float] [-terminate pullup|keeper|float] [-iostd LVTTL|LVCMOS18|LVCMOS18_ANY|LVCMOS25|LVCMOS33|SSTL2_I|SSTL3_I|HSTL_I|LVCMOS15] [-blkfanin ] [--noopendrain] [--nocxt] [--nomdf] [--noxml] [--neweqn] [--holistic] [--noibis] [--htmlrpt] [--libxslt ] [--noselfpinlock] [--readngd_debug] [--write_mapped_network ] [--write_optimized_network ] [--write_xpla_jedec] [--skip_syn] [--pin_spread_out] [--xpla_opt ] [--xpla_debug] [--xstrategy inputs|pterms] [--xinputs ] [--xpterms ] [--readngd] [--partgen] s PK __REGISTRY__/STE/hprep6/PK 鶊v__REGISTRY__/STE/hprep6/regkeysCommandLine C:\Xilinx\10.1\ISE\bin\nt\unwrapped\hprep6.exe -ise C:/midas/mscb/embedded/scs_2001/cpld/scs_2001.ise -s IEEE1149 -i scs_2001 s FormatString hprep6 [-i ] [--intstyle ise|xflow|silent] [-n ] [-tmv ] [-nopullup] [-s ieee1532|IEEE1532|ieee1149|IEEE1149] [-autosig] [--holistic] [--r ] [--a] [--l ] [--q] [--annotate] [--bypass cr2s|CR2S] s PK __REGISTRY__/STE/ngdbuild/PK .!__REGISTRY__/STE/ngdbuild/regkeysCommandLine C:\Xilinx\10.1\ISE\bin\nt\unwrapped\ngdbuild.exe -ise C:/midas/mscb/embedded/scs_2001/cpld/scs_2001.ise -intstyle ise -dd _ngo -i -p xc2c384-TQ144-7 scs_2001.ngc scs_2001.ngd s FormatString ngdbuild [-p ] {-sd } {-l } [-ur ] [-dd ] [-r] [-a] [-u] [-nt timestamp|on|off] [-uc ] [-aul] [-bm ] [-i] [-modular initial|module|assemble] [-intstyle ise|xflow|silent] [-quiet] [-verbose] [-active ] [-pimpath ] {-use_pim } [-insert_keep_hierarchy] [--forcengd] {--n } {--sl } [--global_opt] [--script ] [--incremental] [--csttrans] [] s PK __REGISTRY__/STE/taengine/PK `gg!__REGISTRY__/STE/taengine/regkeysCommandLine taengine -ise C:/midas/mscb/embedded/scs_2001/cpld/scs_2001.ise s FormatString taengine s PK __REGISTRY__/STE/tsim/PK `i-__REGISTRY__/STE/tsim/regkeysCommandLine C:\Xilinx\10.1\ISE\bin\nt\unwrapped\tsim.exe -ise C:/midas/mscb/embedded/scs_2001/cpld/scs_2001.ise -intstyle ise scs_2001 scs_2001.nga s FormatString tsim [--intstyle ise|xflow|silent] [] s PK __REGISTRY__/STE/xst/PK g@ݫ__REGISTRY__/STE/xst/regkeysCommandLine C:\Xilinx\10.1\ISE\bin\nt\unwrapped\xst.exe -ise C:/midas/mscb/embedded/scs_2001/cpld/scs_2001.ise -intstyle ise -ifn C:/midas/mscb/embedded/scs_2001/cpld/scs_2001.xst -ofn C:/midas/mscb/embedded/scs_2001/cpld/scs_2001.syr -finalclean 1 s FormatString xst [-ifn ] [-ofn ] [-ise ] [--quiet] [-intstyle